公开(公告)号：US11800635B2

公开(公告)日：2023-10-24

申请号：US17233200

申请日：2021-04-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jyou Kikura ,  Toshihiro Tada ,  Tadashi Washimori

IPC: H01F27/28 ,  H01G4/008 ,  H01G4/12 ,  H01G4/33 ,  H05K1/02 ,  H05K1/03 ,  H05K1/16

CPC classification number: H05K1/0216 ,  H01F27/2804 ,  H01G4/008 ,  H01G4/12 ,  H01G4/33 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/0792

Abstract: A capacitor is disposed on a substrate that is insulative. An inductor is disposed on the substrate. The inductor includes a conductor pattern having at least one end connected to the capacitor. The capacitor includes a dielectric film that mainly contains the same constituent element as a constituent element mainly contained in the substrate and at least two electrodes that face each other with the dielectric film interposed therebetween.

公开(公告)号：US20180368259A1

公开(公告)日：2018-12-20

申请号：US15626244

申请日：2017-06-19

Applicant: DELL PRODUCTS, L.P.

Inventor： VIJENDERA KUMAR ,  BHYRAV M. MUTNURY ,  V. MALLIKARJUN GOUD

IPC: H05K1/11 ,  H01R12/72

CPC classification number: H05K1/111 ,  H01R12/72 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/025 ,  H05K2201/0792 ,  H05K2201/09154 ,  H05K2201/09381

Abstract: An Information handling system (IHS) includes a circuit board assembly with surface mount technology (SMT) pad structure. Landing pad(s) attached to circuit board substrate have a mounting area that receive an SMT connector pin onto adjacent pair of differential contact strips plated to nonconductive surface and extending longitudinally in parallel alignment. A return current strip is longitudinally aligned, adjacent to the differential contact strips on a first lateral side. The return current strip is connected to a ground plane of the circuit board substrate. Converging narrowing of the adjacent differential contact strip increases separation from a distal end of the return current strip. The separation improves signal integrity by reducing fringe effects, increasing impedance, and quenching resonance. A surface mount device (SMD) has one or more connector pins that are attached to the one or more landing pads to conduct the high-speed communication signal.

公开(公告)号：US09326369B2

公开(公告)日：2016-04-26

申请号：US13921550

申请日：2013-06-19

Applicant: Keithley Instruments, Inc.

Inventor： James A. Niemann ,  Gregory Sobolewski ,  Martin J. Rice ,  Wayne Goeke

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H05K3/30 ,  H05K1/14

CPC classification number: H05K1/0213 ,  H05K1/0225 ,  H05K1/0256 ,  H05K1/142 ,  H05K1/145 ,  H05K3/306 ,  H05K3/4038 ,  H05K3/4697 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09981 ,  Y10T29/49139

Abstract: A device with low dielectric absorption includes a printed circuit board (PCB), a component connection area including a first conductor layered on a top surface of the component connection area and a second conductor layered on a bottom surface of the component connection area, an aperture surrounding the component connection area, a low-leakage component connecting the component connection area to the PCB across the aperture, and a guard composed of a third conductor at least substantially surrounding the aperture on a top surface of the PCB and a fourth conductor at least substantially surrounding the aperture on a bottom surface of the PCB.

Abstract translation: 具有低介电吸收率的器件包括印刷电路板（PCB），包括层叠在部件连接区域的顶表面上的第一导体的部件连接区域和层叠在部件连接区域的底表面上的第二导体， 围绕部件连接区域，将部件连接区域连接到穿过孔的PCB的低泄漏部件以及由至少基本上围绕PCB顶表面上的孔的第三导体组成的防护件和至少 基本上围绕PCB的底表面上的孔。

公开(公告)号：US20150163909A1

公开(公告)日：2015-06-11

申请号：US14000566

申请日：2012-06-19

Applicant: SHENNAN CIRCUITS CO LTD.

Inventor： Chuanzhi Li ,  Hua Miao ,  Zhanhao Xie ,  Jun Peng

IPC: H05K1/11 ,  H05K3/00 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/0298 ,  H05K3/0094 ,  H05K3/4635 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09618 ,  H05K2201/09845 ,  H05K2201/10242 ,  H05K2201/10416 ,  Y10T29/49165

Abstract: A printed circuit board (PCB) a method for processing PCB and an electronic apparatus are provided. The method for processing PCB may include: forming a hole in the PCB, wherein the PCB includes a metal matrix and at least two substrate layers, at least one of the at least two substrate layers has an geoelectric layer thereon; the metal matrix is fixed in a slot provided its the substrate, the formed hole contacts with both the geoelectric layer and the metal matrix; and providing conductive substances in the hole, with the conductive substances in the hole being in contact with the inner geoelectric layer and the metal matrix, so that the inner geoelectric layer and the metal matrix are in conduction with each other. The solutions of the embodiments of the application are beneficial to improve reliability of connection between the geoelectric layer and the metal matrix of the PCB, and improve transmission performance of a high frequency signal.

Abstract translation: 提供印刷电路板（PCB）用于处理PCB和电子设备的方法。 用于处理PCB的方法可以包括：在PCB中形成孔，其中PCB包括金属基体和至少两个基底层，至少两个基底层中的至少一个在其上具有地电层; 金属基体固定在设置其基板的槽中，形成的孔与地电电极和金属基体接触; 并且在孔中提供导电物质，孔中的导电物质与内部地电电极和金属基体接触，使得内部地电电介质层和金属基体彼此导通。 本申请的实施例的解决方案有利于提高PCB上的地电层和金属矩阵之间的连接的可靠性，并提高高频信号的传输性能。

公开(公告)号：US20140262499A1

公开(公告)日：2014-09-18

申请号：US13804575

申请日：2013-03-14

Applicant: BOULDER WIND POWER, INC.

Inventor： James S. Smith ,  James D. Duford ,  Stephane Eisen ,  James D. Jore ,  Brian Sullivan

IPC: H01B5/00 ,  H01R4/00

CPC classification number: H01R4/00 ,  H02K3/26 ,  H02K7/1838 ,  H02K21/24 ,  H05K1/0201 ,  H05K1/0216 ,  H05K1/165 ,  H05K3/462 ,  H05K2201/0792 ,  H05K2201/09227 ,  H05K2201/093 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/09972 ,  H05K2201/10272 ,  H05K2201/10295

Abstract: In some embodiments, a system includes a first portion, a second portion, and a third portion of an electrical conductor. Each portion is electrically coupled to the other two portions. The first, second, and third portions are configured such that substantially no current induced in and/or supplied to the first portion is conducted to the third portion of the electrical conductor. The third portion of the electrical conductor is also thermally coupled to the first and second portions of the electrical conductor. The third portion of the electrical conductor is configured to transfer thermal energy from the first portion of the electrical conductor to an edge portion of the laminated composite assembly.

Abstract translation: 在一些实施例中，系统包括电导体的第一部分，第二部分和第三部分。 每个部分电耦合到另外两个部分。 第一，第二和第三部分被配置为使得基本上没有在第一部分中引入和/或提供给第一部分的电流被传导到电导体的第三部分。 电导体的第三部分也热耦合到电导体的第一和第二部分。 电导体的第三部分被配置为将热能从电导体的第一部分传递到层压复合组件的边缘部分。

公开(公告)号：US08507802B1

公开(公告)日：2013-08-13

申请号：US12113617

申请日：2008-05-01

Applicant: William Knauer

Inventor： William Knauer

IPC: H05K1/00

CPC classification number: H05K1/0213 ,  G01R19/0092 ,  H05K1/0218 ,  H05K1/0262 ,  H05K3/368 ,  H05K2201/0191 ,  H05K2201/041 ,  H05K2201/0792

Abstract: Provided is printed circuit board for minimizing dielectric losses experienced by a low-current portion of an electric circuit. The printed circuit board includes a first substrate supporting an electrically-conductive material patterned to form a conductive pathway between electric circuit components, and a surface-mount guard pad provided on a substantially-planar exposed surface of the first substrate and covering at least an area of the exposed surface including a footprint of the low-current portion on the first substrate. A second substrate is also provided with one or more electrically conductive pads that are surface mounted to the guard pad to couple the second substrate to the guard pad. The second substrate also supports a signal trace included in the low-current region for conducting a low-current signal.

Abstract translation: 提供了用于最小化电路的低电流部分所经历的介电损耗的印刷电路板。 印刷电路板包括支撑图案化以在电路部件之间形成导电路径的导电材料的第一基板和设置在第一基板的基本上平坦的暴露表面上的表面安装保护垫，并且覆盖至少一个区域 所述暴露表面包括所述第一基底上的所述低电流部分的覆盖区。 第二基板还设置有一个或多个导电焊盘，其表面安装到保护焊盘以将第二衬底耦合到保护焊盘。 第二基板还支持包括在低电流区域中的用于传导低电流信号的信号迹线。

公开(公告)号：US08040930B2

公开(公告)日：2011-10-18

申请号：US12189930

申请日：2008-08-12

Applicant: Kazuhisa Mizusako ,  Kiyoto Sudo

Inventor： Kazuhisa Mizusako ,  Kiyoto Sudo

IPC: H01S3/00 ,  H05K1/14

CPC classification number: H01S5/042 ,  H01S3/109 ,  H01S5/0427 ,  H01S5/0428 ,  H01S5/14 ,  H05B33/0818 ,  H05K1/0228 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/10106 ,  H05K2201/10166 ,  H05K2201/10545 ,  Y02P70/611

Abstract: A drive circuit for driving a semiconductor light emitting element includes a board, a first pattern formed in a first layer of the board so as to be electrically connected to an anode of the semiconductor light emitting element, and a second pattern formed in a second layer of the board so as to be electrically connected to a cathode of the semiconductor light emitting element, and the first pattern and the second pattern are formed so as to overlap with each other when viewed in a direction along a normal line of the board.

Abstract translation: 用于驱动半导体发光元件的驱动电路包括基板，形成在基板的第一层中以与半导体发光元件的阳极电连接的第一图案，以及形成在第二层中的第二图案 以便电连接到半导体发光元件的阴极，并且当沿着沿着基板的法线的方向观察时，第一图案和第二图案形成为彼此重叠。

公开(公告)号：US20100226112A1

公开(公告)日：2010-09-09

申请号：US12783478

申请日：2010-05-19

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: H05K9/00

CPC classification number: H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract translation: 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

公开(公告)号：US07764512B2

公开(公告)日：2010-07-27

申请号：US11451292

申请日：2006-06-12

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: H05K7/18

CPC classification number: H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract translation: 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

公开(公告)号：US07742276B2

公开(公告)日：2010-06-22

申请号：US11950381

申请日：2007-12-04

Applicant: Chien-Min Hsu ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Chien-Min Hsu ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: H01G4/228

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.

Abstract translation: 本发明涉及一种用于降低层叠电容器的等效串联电感（ESL）的布线结构。 层叠电容器包括多个导电层，沿层叠电容器的厚度方向延伸的电力通孔，并且从顶部导电层延伸至底部导电层，沿着层叠电容器的厚度方向延伸的接地通孔 并布置成从顶部导电层延伸到底部导电层。 导电层包括一组第一导电层和一组第二导电层。 电源通孔电耦合到第一导电层，并且接地通孔电耦合到第二导电层。 层叠电容器还包括电源通孔和接地通孔之间的补充通路。 补充通孔的长度要短于电源通孔和接地通孔。 辅助通孔电耦合到第一导电层和第二导电层之一。