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    Memory Tracing in an Emulation Environment
    1.
    发明申请
    Memory Tracing in an Emulation Environment 失效
    在仿真环境中的内存跟踪

    公开(公告)号：US20080288719A1

    公开(公告)日：2008-11-20

    申请号：US12094392

    申请日：2007-02-21

    申请人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge ,  Cyril Quennesson

    发明人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge ,  Cyril Quennesson

    IPC分类号： G06F12/16

    CPC分类号： G06F17/5027

    摘要： A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.

    摘要翻译： 公开了一种在硬件仿真器中跟踪存储器的系统和方法。 在一个方面，第一随机存取存储器用于在仿真期间存储与用户设计相关联的数据。 在任何期望的时间点，第一随机存取存储器的内容被捕获在第二随机存取存储器中。 在捕获之后，第二随机存取存储器的内容被复制到可见性系统。 在复制期间，用户设计可以修改第一随机存取存储器中的数据，同时第二随机存取存储器内的捕获内容保持不可修改，使得所捕获的内容不受损害。 在另一方面，不同尺寸的存储器在仿真器中以模拟用户模型。 较大的存储器端口被监视以重建存储器的内容，而较小的存储器被捕获在快照RAM中。 跟踪存储器的两种不同模式一起用于提供整个用户存储器的用户的可见性。

    Memory tracing in an emulation environment
    2.
    发明授权
    Memory tracing in an emulation environment 失效
    在仿真环境中的内存跟踪

    公开(公告)号：US08108198B2

    公开(公告)日：2012-01-31

    申请号：US12094392

    申请日：2007-02-21

    申请人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge ,  Cyril Quennesson

    发明人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge ,  Cyril Quennesson

    IPC分类号： G06F9/445 ,  G06F3/00

    CPC分类号： G06F17/5027

    摘要： A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.

    摘要翻译： 公开了一种在硬件仿真器中跟踪存储器的系统和方法。 在一个方面，第一随机存取存储器用于在仿真期间存储与用户设计相关联的数据。 在任何期望的时间点，第一随机存取存储器的内容被捕获在第二随机存取存储器中。 在捕获之后，第二随机存取存储器的内容被复制到可见性系统。 在复制期间，用户设计可以修改第一随机存取存储器中的数据，同时第二随机存取存储器内的捕获内容保持不可修改，使得所捕获的内容不受损害。 在另一方面，不同尺寸的存储器在仿真器中以模拟用户模型。 较大的存储器端口被监视以重建存储器的内容，而较小的存储器被捕获在快照RAM中。 跟踪存储器的两种不同模式一起用于提供整个用户存储器的用户的可见性。

    Communication scheme between programmable sub-cores in an emulation environment
    3.
    发明授权
    Communication scheme between programmable sub-cores in an emulation environment 有权
    在仿真环境中的可编程子核之间的通信方案

    公开(公告)号：US08352242B2

    公开(公告)日：2013-01-08

    申请号：US12094401

    申请日：2007-02-21

    申请人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge

    发明人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5027

    摘要： A system and method are disclosed for communicating in a programmable core. The programmable core is within a single integrated circuit and is divided into multiple independent sub-cores. The sub-cores are coupled together using a multiplexer based network. In another aspect, the multiplexer-based network includes multiplexers associated with some of the sub-cores for sending data and demultiplexers associated with other sub-cores for receiving data. In yet another aspect, a clock is included in the multiplexer-based network for synchronizing communication between the multiplexers and demultiplexers.

    摘要翻译： 公开了用于在可编程核心中进行通信的系统和方法。 可编程内核在单个集成电路内，分为多个独立子核。 子核使用基于复用器的网络耦合在一起。 在另一方面，基于多路复用器的网络包括与一些子核相关联的多路复用器，用于发送与用于接收数据的其他子核相关联的数据和解复用器。 在另一方面，在基于复用器的网络中包括时钟，用于同步多路复用器和解复用器之间的通信。

    Communication Scheme Between Programmable Sub-Cores in an Emulation Environment
    4.
    发明申请
    Communication Scheme Between Programmable Sub-Cores in an Emulation Environment 有权
    仿真环境中的可编程子核心之间的通信方案

    公开(公告)号：US20080288236A1

    公开(公告)日：2008-11-20

    申请号：US12094401

    申请日：2007-02-21

    申请人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge

    发明人： Peer Schmitt ,  Philippe Diehl ,  Charles Selvidge

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5027

    摘要： A system and method are disclosed for communicating in a programmable core. The programmable core is within a single integrated circuit and is divided into multiple independent sub-cores. The sub-cores are coupled together using a multiplexer based network. In another aspect, the multiplexer-based network includes multiplexers associated with some of the sub-cores for sending data and demultiplexers associated with other sub-cores for receiving data. In yet another aspect, a clock is included in the multiplexer-based network for synchronizing communication between the multiplexers and demultiplexers.

    摘要翻译： 公开了用于在可编程核心中进行通信的系统和方法。 可编程内核在单个集成电路内，分为多个独立子核。 子核使用基于复用器的网络耦合在一起。 在另一方面，基于多路复用器的网络包括与一些子核相关联的多路复用器，用于发送与用于接收数据的其他子核相关联的数据和解复用器。 在另一方面，在基于复用器的网络中包括时钟，用于同步多路复用器和解复用器之间的通信。

    Memory-based trigger generation scheme in an emulation environment
    6.
    发明授权
    Memory-based trigger generation scheme in an emulation environment 有权
    在仿真环境中基于内存的触发器生成方案

    公开(公告)号：US08868974B2

    公开(公告)日：2014-10-21

    申请号：US13361759

    申请日：2012-01-30

    申请人： Gregoire Brunot ,  Charles Selvidge

    发明人： Gregoire Brunot ,  Charles Selvidge

    IPC分类号： G06F11/00 ,  G06F17/50

    CPC分类号： G06F17/5022 ,  G06F11/261

    摘要： A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration.

    摘要翻译： 公开了用于在硬件仿真器内产生触发的系统和方法。 该系统允许在仿真期间对触发器生成方案进行动态重新配置。 在一个方面，输入探针信号从仿真器内的集成电路的地址端口接收到存储器。 存储器从数据端口输出数据，数据至少部分由输入探测信号寻址。 从数据端口输出的数据可以通过进一步的组合逻辑发送，或直接连接到逻辑分析仪，并表示触发信息。 在另一方面，可以在仿真期间动态地重新配置触发器生成方案。 例如，在存储器是双端口RAM的情况下，仿真主机可以写入存储器以执行重新配置。

    MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT
    7.
    发明申请
    MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT 有权
    在模拟环境中基于记忆的触发器生成方案

    公开(公告)号：US20120221316A1

    公开(公告)日：2012-08-30

    申请号：US13361759

    申请日：2012-01-30

    申请人： Gregoire Brunot ,  Charles Selvidge

    发明人： Gregoire Brunot ,  Charles Selvidge

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5022 ,  G06F11/261

    摘要： A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration.

    摘要翻译： 公开了用于在硬件仿真器内产生触发的系统和方法。 该系统允许在仿真期间对触发器生成方案进行动态重新配置。 在一个方面，输入探测信号在仿真器内的集成电路的地址端口接收到存储器。 存储器从数据端口输出数据，数据至少部分由输入探测信号寻址。 从数据端口输出的数据可以通过进一步的组合逻辑发送，或直接连接到逻辑分析仪，并表示触发信息。 在另一方面，可以在仿真期间动态地重新配置触发器生成方案。 例如，在存储器是双端口RAM的情况下，仿真主机可以写入存储器以执行重新配置。

    Acyclic modeling of combinational loops
    8.
    发明申请
    Acyclic modeling of combinational loops 有权
    组合环的非循环建模

    公开(公告)号：US20060123300A1

    公开(公告)日：2006-06-08

    申请号：US11068036

    申请日：2005-03-01

    申请人： Amit Gupta ,  Charles Selvidge

    发明人： Amit Gupta ,  Charles Selvidge

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G06F17/505 ,  G06F17/5059

    摘要： Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops.

    摘要翻译： 本发明的方面涉及将非振荡组合环转换为非循环电路。 组合环可以被建模为状态保持元件，其中使用边缘敏感锁存器来断开非振荡环路。 除了提供一种初始仅由门组成的组合循环（即，最初不包括任何状态保持元件）的方式之外，还可以转换具有通过用户锁存器的路径的循环。 所提出的方法可以与小循环和大循环一起使用。

    Software state replay
    9.
    发明申请
    Software state replay 有权

    公开(公告)号：US20060074622A1

    公开(公告)日：2006-04-06

    申请号：US11181036

    申请日：2005-07-12

    申请人： David Scott ,  Charles Selvidge ,  Joshua Marantz ,  Frederic Reblewski

    发明人： David Scott ,  Charles Selvidge ,  Joshua Marantz ,  Frederic Reblewski

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5027 ,  G06F11/3636 ,  G06F11/3692

    摘要： A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.

    Biodiesel fuel blend
    10.
    发明授权
    Biodiesel fuel blend 有权
    生物柴油燃料混合

    公开(公告)号：US07964000B2

    公开(公告)日：2011-06-21

    申请号：US11674887

    申请日：2007-02-14

    申请人： Charles Selvidge

    发明人： Charles Selvidge

    IPC分类号： C10L1/18

    CPC分类号： C10L1/026 ,  C10G2300/1011 ,  C10L1/19 ,  Y02E50/13 ,  Y02P30/20

    摘要： Biodiesel fuel blends with improved low temperature filterability include a biodiesel source with reduced glycerin contaminants, and reduced monopalmitin and monostearin contaminants, or with cold filter characteristics equivalent with the base diesel.

    摘要翻译： 具有改进的低温过滤性的生物柴油燃料混合物包括具有降低的甘油污染物的生物柴油来源和降低的单棕榈酸酯和单硬脂酸酯污染物，或具有与基础柴油相当的冷过滤特性。