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公开(公告)号：US08108198B2
公开(公告)日：2012-01-31
申请号：US12094392
申请日：2007-02-21
CPC分类号： G06F17/5027
摘要： A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.
摘要翻译： 公开了一种在硬件仿真器中跟踪存储器的系统和方法。 在一个方面，第一随机存取存储器用于在仿真期间存储与用户设计相关联的数据。 在任何期望的时间点，第一随机存取存储器的内容被捕获在第二随机存取存储器中。 在捕获之后，第二随机存取存储器的内容被复制到可见性系统。 在复制期间，用户设计可以修改第一随机存取存储器中的数据，同时第二随机存取存储器内的捕获内容保持不可修改，使得所捕获的内容不受损害。 在另一方面，不同尺寸的存储器在仿真器中以模拟用户模型。 较大的存储器端口被监视以重建存储器的内容，而较小的存储器被捕获在快照RAM中。 跟踪存储器的两种不同模式一起用于提供整个用户存储器的用户的可见性。
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2.发明授权Communication scheme between programmable sub-cores in an emulation environment 有权在仿真环境中的可编程子核之间的通信方案公开(公告)号：US08352242B2
公开(公告)日：2013-01-08
申请号：US12094401
申请日：2007-02-21
申请人： Peer Schmitt , Philippe Diehl , Charles Selvidge
发明人： Peer Schmitt , Philippe Diehl , Charles Selvidge
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A system and method are disclosed for communicating in a programmable core. The programmable core is within a single integrated circuit and is divided into multiple independent sub-cores. The sub-cores are coupled together using a multiplexer based network. In another aspect, the multiplexer-based network includes multiplexers associated with some of the sub-cores for sending data and demultiplexers associated with other sub-cores for receiving data. In yet another aspect, a clock is included in the multiplexer-based network for synchronizing communication between the multiplexers and demultiplexers.
摘要翻译： 公开了用于在可编程核心中进行通信的系统和方法。 可编程内核在单个集成电路内，分为多个独立子核。 子核使用基于复用器的网络耦合在一起。 在另一方面，基于多路复用器的网络包括与一些子核相关联的多路复用器，用于发送与用于接收数据的其他子核相关联的数据和解复用器。 在另一方面，在基于复用器的网络中包括时钟，用于同步多路复用器和解复用器之间的通信。
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公开(公告)号：US20080288719A1
公开(公告)日：2008-11-20
申请号：US12094392
申请日：2007-02-21
IPC分类号： G06F12/16
CPC分类号： G06F17/5027
摘要： A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.
摘要翻译： 公开了一种在硬件仿真器中跟踪存储器的系统和方法。 在一个方面，第一随机存取存储器用于在仿真期间存储与用户设计相关联的数据。 在任何期望的时间点，第一随机存取存储器的内容被捕获在第二随机存取存储器中。 在捕获之后，第二随机存取存储器的内容被复制到可见性系统。 在复制期间，用户设计可以修改第一随机存取存储器中的数据，同时第二随机存取存储器内的捕获内容保持不可修改，使得所捕获的内容不受损害。 在另一方面，不同尺寸的存储器在仿真器中以模拟用户模型。 较大的存储器端口被监视以重建存储器的内容，而较小的存储器被捕获在快照RAM中。 跟踪存储器的两种不同模式一起用于提供整个用户存储器的用户的可见性。
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4.发明申请Communication Scheme Between Programmable Sub-Cores in an Emulation Environment 有权仿真环境中的可编程子核心之间的通信方案公开(公告)号：US20080288236A1
公开(公告)日：2008-11-20
申请号：US12094401
申请日：2007-02-21
申请人： Peer Schmitt , Philippe Diehl , Charles Selvidge
发明人： Peer Schmitt , Philippe Diehl , Charles Selvidge
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A system and method are disclosed for communicating in a programmable core. The programmable core is within a single integrated circuit and is divided into multiple independent sub-cores. The sub-cores are coupled together using a multiplexer based network. In another aspect, the multiplexer-based network includes multiplexers associated with some of the sub-cores for sending data and demultiplexers associated with other sub-cores for receiving data. In yet another aspect, a clock is included in the multiplexer-based network for synchronizing communication between the multiplexers and demultiplexers.
摘要翻译： 公开了用于在可编程核心中进行通信的系统和方法。 可编程内核在单个集成电路内，分为多个独立子核。 子核使用基于复用器的网络耦合在一起。 在另一方面，基于多路复用器的网络包括与一些子核相关联的多路复用器，用于发送与用于接收数据的其他子核相关联的数据和解复用器。 在另一方面，在基于复用器的网络中包括时钟，用于同步多路复用器和解复用器之间的通信。
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公开(公告)号：US20070045789A1
公开(公告)日：2007-03-01
申请号：US11553532
申请日：2006-10-27
IPC分类号： H01L23/495
摘要： In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
摘要翻译： 在具有多个芯片的仿真系统中，在芯片之间通信的数据需要同步。 接收器芯片可以推送或拉出来自发射器芯片的输入数据，以便与接收机时钟同步。 也可以调整发射器和接收器芯片之间的链路上的意外延迟。
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公开(公告)号：US07823001B2
公开(公告)日：2010-10-26
申请号：US11553532
申请日：2006-10-27
摘要： In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
摘要翻译： 在具有多个芯片的仿真系统中，在芯片之间通信的数据需要同步。 接收器芯片可以推送或拉出来自发射器芯片的输入数据，以便与接收机时钟同步。 也可以调整发射器和接收器芯片之间的链路上的意外延迟。
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公开(公告)号：US20050102545A1
公开(公告)日：2005-05-12
申请号：US10702042
申请日：2003-11-06
摘要： In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
摘要翻译： 在具有多个芯片的仿真系统中，在芯片之间通信的数据需要同步。 接收器芯片可以推送或拉出来自发射器芯片的输入数据，以便与接收机时钟同步。 也可以调整发射器和接收器芯片之间的链路上的意外延迟。
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公开(公告)号：US07924845B2
公开(公告)日：2011-04-12
申请号：US10673665
申请日：2003-09-30
CPC分类号： G06F11/261 , G06F17/5027
摘要： Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.
摘要翻译： 消息发送和接收块被提供给仿真系统的仿真IC和可重配置互连IC，以减少关键仿真信号的复用传输延迟。 相应的消息发送块和消息接收块中的每一个被提供有信号状态值包含调度以控制消息发送和接收块的操作。 信号状态包含调度要求消息内的一些信号比消息内的其他信号更频繁地发送。 在一些实施例中，奇偶校验值被实现为消息的一部分并且被包括在信号状态包含调度中。
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公开(公告)号：US07286976B2
公开(公告)日：2007-10-23
申请号：US10458176
申请日：2003-06-10
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.
摘要翻译： 用于仿真包括在线存储器的电路设计的方法和装置。 可重构逻辑资源的集合被配置为模拟电路的逻辑元件，其中电路可以包括多个逻辑元件。 存储器资源被配置为模拟在线存储器的一部分。 可配置互连资源被配置为通过存储器访问仲裁器将可配置逻辑资源集合互连到存储器资源。 存储器访问仲裁器被配置为根据相关联的优先级级别在仿真周期中通过可重配置逻辑资源的集合来仲裁和序列化存储器资源的访问。 可重配置逻辑资源组的优先级可以取决于该组可重配置逻辑资源的时序要求以及该电路的相关逻辑元件的定时特性。
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公开(公告)号：US07231538B2
公开(公告)日：2007-06-12
申请号：US10702042
申请日：2003-11-06
摘要： In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
摘要翻译： 在具有多个芯片的仿真系统中，在芯片之间通信的数据需要同步。 接收器芯片可以推送或拉出来自发射器芯片的输入数据，以便与接收机时钟同步。 也可以调整发射器和接收器芯片之间的链路上的意外延迟。
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