公开(公告)号：US5872390A

公开(公告)日：1999-02-16

申请号：US911542

申请日：1997-08-14

申请人： Pei-Ing Paul Lee ,  William Alan Klaasen ,  Alexander Mitwalsky

发明人： Pei-Ing Paul Lee ,  William Alan Klaasen ,  Alexander Mitwalsky

IPC分类号： H01H85/00 ,  H01L21/82 ,  H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L2924/0002

摘要： A fuse window structure and method for forming the same for a semiconductor device with a fuse and a cutting site on the fuse, the structure having (1) a first oxide region substantially in register with the cutting site, the first oxide region having a first thickness, (2) a second oxide region substantially in register with a first land generally surrounding the cutting site, the first land generally in register with the fuse, the second region having a second thickness, and (3) a third oxide region substantially in register with a second land generally surrounding the fuse, the third region having a third thickness different than the first thickness. Different fuse window structures are formed by using etch stops with different configurations, each configuration differing with regard to coverage of the three oxide regions.

摘要翻译： 一种用于在熔丝上具有熔丝和切割部位的半导体器件形成熔丝窗结构和方法，所述结构具有（1）与所述切割部位基本上对准的第一氧化物区域，所述第一氧化物区域具有第一 厚度，（2）基本上与通常围绕切割位置的第一焊盘对准的第二氧化物区域，第一焊盘通常与熔丝对准，第二区域具有第二厚度，以及（3）基本上在 与通常围绕熔丝的第二焊盘对准，第三区域具有不同于第一厚度的第三厚度。 通过使用具有不同配置的蚀刻停止件形成不同的熔丝窗结构，每个配置关于三个氧化物区域的覆盖范围不同。

公开(公告)号：US6091273A

公开(公告)日：2000-07-18

申请号：US914857

申请日：1997-08-19

申请人： Kerry Bernstein ,  Daniel Charles Edelstein ,  William Alan Klaasen ,  Wilbur David Pricer

发明人： Kerry Bernstein ,  Daniel Charles Edelstein ,  William Alan Klaasen ,  Wilbur David Pricer

IPC分类号： G11C17/18 ,  H03K17/687 ,  H03L5/00

CPC分类号： H03K17/6872 ,  G11C17/18

摘要： A voltage limiting circuit for fuse technology. The voltage limiting circuit is coupled to the two terminals. The voltage limiting circuit is responsive to a fuse blow through a low impedance sensing circuit, and then minimizes the voltage across the fuse gap that is created by the fuse blow. Thus, the invention prevents dendritic growth and corrosion in copper or similar types of fuses.

摘要翻译： 一种用于保险丝技术的限压电路。 电压限制电路耦合到两个端子。 电压限制电路响应于通过低阻抗感测电路的保险丝熔断，然后使由保险丝熔断产生的熔丝间隙上的电压最小化。 因此，本发明防止了铜或类似类型的保险丝中的树枝状生长和腐蚀。

公开(公告)号：US5898706A

公开(公告)日：1999-04-27

申请号：US846989

申请日：1997-04-30

申请人： Roger Aime Dufresne ,  Charles William Griffin ,  Chorng-Lii Hwang ,  William Alan Klaasen ,  Alvin Wayne Strong

发明人： Roger Aime Dufresne ,  Charles William Griffin ,  Chorng-Lii Hwang ,  William Alan Klaasen ,  Alvin Wayne Strong

IPC分类号： G01R31/28 ,  G01R31/12

CPC分类号： G01R31/2877 ,  G01R31/2856

摘要： The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.

摘要翻译： 本发明涉及一种用于集成电路的可靠性测试的装置和方法。 本发明提供了一种用于测试集成电路的栅极和节点电介质的测试结构和方法，其中自加热栅结构与产品结构本身集成。 产品结构内的所选导线用作加热元件，以提供集成电路的温度应力。 局部自加热门结构是产品芯片的组成部分。 因此，测试结构的蚀刻和沉积特性保持与产品本身的蚀刻和沉积特性相同。 由于低压技术使得由于电压应力而难以获得显着的加速度，所以可以使用温度应力来增加加速度。