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公开(公告)号：US5843363A
公开(公告)日：1998-12-01
申请号：US414241
申请日：1995-03-31
IPC分类号： H01L21/306 , B23K26/06 , B23K26/18 , B23K26/40 , H01L21/268 , H01L21/311 , H05K3/00 , B23K26/00 , B32B31/18
CPC分类号： B23K26/0661 , B23K26/18 , B23K26/40 , H01L21/311 , H01L21/31105 , B23K2201/40 , B23K2203/172 , B23K2203/50 , H05K3/0017
摘要： A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection includes monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.
摘要翻译： 在不蚀刻下面的导电材料层的情况下，通过一个或多个介电材料层进行烧蚀蚀刻的方法包括选择参数，由此当达到导电材料层时，消融过程自动停止，或者监测所需程度的终点检测过程 的消融。 选择的参数是电介质层与导电材料层的吸收率。 终点检测包括监测从工件反射的辐射能或从工件烧蚀的材料的内容物。
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公开(公告)号：US5609148A
公开(公告)日：1997-03-11
申请号：US414871
申请日：1995-03-31
CPC分类号： B23D57/0023 , B28D5/0094 , B28D5/045
摘要： A method and apparatus for dicing a semiconductor wafer in which the wafer is bowed or bent by forcing it into contact with a spherical surface having parallel grooves therein and in which an array of parallel wire saws that are in registration with the grooves is forced against the wafer for sawing parallel channels therethrough. A second array of parallel wire saws that are orthogonal to the wires of the first array is provided spaced therefrom for sawing parallel channels through the wafer that are orthogonal to the channels produced by the first array of parallel wire saws.
摘要翻译： 一种用于切割半导体晶片的方法和装置，其中晶片通过迫使其与其中具有平行凹槽的球面接触而弯曲或弯曲，并且其中与槽对准的平行线锯阵列被迫抵抗 用于锯切平行通道的晶片。 与第一阵列的导线垂直的第二平行线锯阵列与其间隔开设置，用于锯切通过晶片的平行通道，其与由第一平行线锯阵列产生的通道正交。
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公开(公告)号：US5872390A
公开(公告)日：1999-02-16
申请号：US911542
申请日：1997-08-14
IPC分类号： H01H85/00 , H01L21/82 , H01L23/525 , H01L23/58 , H01L29/00
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002
摘要： A fuse window structure and method for forming the same for a semiconductor device with a fuse and a cutting site on the fuse, the structure having (1) a first oxide region substantially in register with the cutting site, the first oxide region having a first thickness, (2) a second oxide region substantially in register with a first land generally surrounding the cutting site, the first land generally in register with the fuse, the second region having a second thickness, and (3) a third oxide region substantially in register with a second land generally surrounding the fuse, the third region having a third thickness different than the first thickness. Different fuse window structures are formed by using etch stops with different configurations, each configuration differing with regard to coverage of the three oxide regions.
摘要翻译： 一种用于在熔丝上具有熔丝和切割部位的半导体器件形成熔丝窗结构和方法，所述结构具有（1）与所述切割部位基本上对准的第一氧化物区域，所述第一氧化物区域具有第一 厚度，（2）基本上与通常围绕切割位置的第一焊盘对准的第二氧化物区域，第一焊盘通常与熔丝对准，第二区域具有第二厚度，以及（3）基本上在 与通常围绕熔丝的第二焊盘对准，第三区域具有不同于第一厚度的第三厚度。 通过使用具有不同配置的蚀刻停止件形成不同的熔丝窗结构，每个配置关于三个氧化物区域的覆盖范围不同。
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公开(公告)号：US06195300B1
公开(公告)日：2001-02-27
申请号：US09536185
申请日：2000-03-24
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： According to one aspect of the invention, there is provided a method for refreshing memory cells in semiconductor memories. The method includes the steps of providing a semiconductor memory having memory cells and redundancy memory cells in at least one memory array and an associated redundancy memory array, respectively. The memory cells and the redundancy memory cells are independently refreshed, using addresses generated by a row address counter and a redundancy address counter, respectively. The method optionally includes the step of disabling redundancy wordlines coupled to unused redundancy memory cells, using a master fuse signal corresponding to a master fuse of the semiconductor memory.
摘要翻译： 根据本发明的一个方面，提供一种刷新半导体存储器中的存储单元的方法。 该方法包括以下步骤：分别在至少一个存储器阵列和相关联的冗余存储器阵列中提供具有存储器单元和冗余存储单元的半导体存储器。 使用地址计数器和冗余地址计数器分别产生的地址，独立刷新存储单元和冗余存储单元。 该方法可选地包括使用与半导体存储器的主熔丝相对应的主熔丝信号来禁用耦合到未使用的冗余存储器单元的冗余字线的步骤。
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公开(公告)号：US5589706A
公开(公告)日：1996-12-31
申请号：US455811
申请日：1995-05-31
申请人： Alexander Mitwalsky , James G. Ryan
发明人： Alexander Mitwalsky , James G. Ryan
IPC分类号： B23K26/00 , B23K26/38 , H01L21/304 , H01L21/82 , H01L21/822 , H01L23/525 , H01L27/04 , H01L27/10
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10S438/926 , Y10S438/952
摘要： An improved etch behavior is promoted to generate vertical sidewalls for fuse links that will promote reliable and repeatable laser cutting of the fuse links. In one embodiment, dummy structures are added adjacent to fuse links in order to obtain the vertical sidewalls for reliable fuse deletion. The dummy structures form no part of the fuse or circuit structure but, because of the proximity of the dummy structures to the fuse links, vertical sidewalls are promoted in a reactive ion etch which is used to form the fuse array. In another embodiment, the vertical sidewalls of the fuse links are achieved in a damascene process in which grooves are formed in an oxide layer and filled with a metal. These grooves correspond to the fuse links and alternating dummy structures. Once filled, the surface is planarized using a chemical-mechanical process. The dummy structures provide reinforcement for the metallization (metal and dielectric film), maintaining the integrity of the metallization. In both embodiments, the vertical sidewalls and constant height of the resulting fuse links promote reliable laser cutting.
摘要翻译： 促进改进的蚀刻行为以产生熔丝链的垂直侧壁，这将促进熔丝链的可靠和可重复的激光切割。 在一个实施例中，虚拟结构被添加到熔丝链附近，以便获得用于可靠熔丝删除的垂直侧壁。 虚拟结构不构成熔丝或电路结构的一部分，但是由于虚设结构与熔丝链的接近，因此在用于形成熔丝阵列的反应离子蚀刻中促进垂直侧壁。 在另一个实施例中，熔丝链的垂直侧壁在镶嵌工艺中实现，其中凹槽形成在氧化物层中并填充有金属。 这些槽对应于熔断体和交替的虚拟结构。 填充后，使用化学 - 机械方法将表面平坦化。 虚拟结构为金属化（金属和介电膜）提供加强，保持金属化的完整性。 在两个实施例中，所产生的熔断体的垂直侧壁和恒定的高度促进了可靠的激光切割。
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公开(公告)号：US06376911B1
公开(公告)日：2002-04-23
申请号：US08518209
申请日：1995-08-23
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A final passivation structure for a semiconductor device having conductive lines formed on a surface of the semiconductor device, comprising a planarized layer covering the surface and also covering the conductive lines, and a diffusion barrier covering the planarized layer. Alternately, the planarized layer may partially cover the conductive lines.
摘要翻译： 一种半导体器件的最终钝化结构，其具有形成在半导体器件的表面上的导线，包括覆盖该表面并覆盖该导电线的平坦化层，以及覆盖该平坦化层的扩散阻挡层。 或者，平坦化层可以部分地覆盖导电线。
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公开(公告)号：US5776826A
公开(公告)日：1998-07-07
申请号：US642983
申请日：1996-05-06
IPC分类号： H01L21/301 , H01L23/485 , H01L23/525 , H05K3/06
CPC分类号： H01L24/05 , H01L23/5256 , H01L23/585 , H01L24/03 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01055 , H01L2924/01074 , H01L2924/14
摘要： A simplified crack stop formation compatible with shallow fuse etch processes which are utilized for modern low-cost redundancy designs using upper level metal fuses. A modified last level metallization (LLM) etch according to the invention allows a high-productivity single step bondpad/fuse/crack stop etch. The stack of metal films formed at the edge of the dicing channel is readily removed with a modified LLM etch prior to dicing causing the insulator films covering the dicing channel to be physically separated from the insulators coating the electrically active chip areas. The separation prevents cracks that could propagate through the insulators of the dicing channel in to the active chip.
摘要翻译： 与使用上层金属保险丝的现代低成本冗余设计中使用的浅熔断体蚀刻工艺相容的简化裂缝停止形成。 根据本发明的经修改的最后一级金属化（LLM）蚀刻允许高生产率单步焊接层/熔丝/裂纹停止蚀刻。 形成在切割通道的边缘处的金属膜堆叠在切割之前通过改进的LLM蚀刻容易地移除，使得覆盖切割通道的绝缘膜与涂覆电活性芯片区域的绝缘体物理分离。 该分离防止可能通过切割通道的绝缘体传播到有源芯片的裂纹。
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公开(公告)号：US5766497A
公开(公告)日：1998-06-16
申请号：US829370
申请日：1997-03-31
IPC分类号： H01L21/306 , B23K26/06 , B23K26/18 , B23K26/40 , H01L21/268 , H01L21/311 , H05K3/00 , B44C1/22 , H01L21/00
CPC分类号： B23K26/0661 , B23K26/18 , B23K26/40 , H01L21/311 , H01L21/31105 , B23K2201/40 , B23K2203/172 , B23K2203/50 , H05K3/0017
摘要： A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection comprises monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.
摘要翻译： 在不蚀刻下面的导电材料层的情况下，通过一个或多个介电材料层进行烧蚀蚀刻的方法包括选择参数，由此当达到导电材料层时，消融过程自动停止，或者监测所需程度的终点检测过程 的消融。 选择的参数是电介质层与导电材料层的吸收率。 终点检测包括监测从工件反射的辐射能或从工件烧蚀的材料的内容物。
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