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公开(公告)号：US08432959B2
公开(公告)日：2013-04-30
申请号：US11930814
申请日：2007-10-31
CPC分类号： H04L25/0262 , H04L25/03006 , H04L25/03057 , H04L2025/03375 , H04L2025/03535 , H04L2025/03726
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.
摘要翻译： 提供了用于均衡接收信号的方法和装置。 通过更新一个或多个均衡参数来使接收信号相等; 以及如果在均衡步骤期间检测到一个或多个预定义的限定条件，则丢弃所述更新的均衡参数。 如果在平衡步骤期间未检测到预定义的限定条件，则可以使用更新的均衡参数来选择性地均衡所接收的信号。 如果在均衡步骤期间未检测到一个或多个预定义限定条件，则可以可选地存储更新的均衡参数。
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公开(公告)号：US08315298B2
公开(公告)日：2012-11-20
申请号：US11930780
申请日：2007-10-31
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译： 提供了用于均衡接收信号的方法和装置。 接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。 均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或 都）。
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公开(公告)号：US07765078B2
公开(公告)日：2010-07-27
申请号：US11967619
申请日：2007-12-31
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。
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4.发明申请METHOD AND APPARATUS FOR DECISION-FEEDBACK EQUALIZATION USING SINGLE-SIDED EYE WITH GLOBAL MINIMUM CONVERGENCE 有权使用单眼眼睛进行决策反馈均衡的方法和装置与全球最小的融合公开(公告)号：US20080080611A1
公开(公告)日：2008-04-03
申请号：US11686148
申请日：2007-03-14
IPC分类号： H04L5/16
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for decision-feedback equalization with global minimum convergence. A threshold position of one or more DFE latches employed by a decision-feedback equalizer is determined by obtaining a plurality of samples of a single-sided data eye using at least one decision latch and at least one roaming latch; comparing the samples obtained by the at least one decision latch and at least one roaming latch to identify an upper and lower voltage boundary of the single-sided data eye; and determining a threshold position of the one or more DFE latches based on the upper and lower voltage boundaries. The comparison can optionally comprise obtaining an exclusive or (XOR) of the samples obtained by the at least one decision latch and at least one roaming latch. The XOR comparison positions an opening for the single-sided data eye at a zero hit count
摘要翻译： 提供了用于具有全局最小收敛的判决反馈均衡的方法和装置。 通过使用至少一个判定锁存器和至少一个漫游锁存器获得单面数据眼睛的多个采样来确定由判决反馈均衡器采用的一个或多个DFE锁存器的阈值位置; 将由所述至少一个判定锁存器获得的样本和至少一个漫游锁存器进行比较，以识别所述单侧数据眼睛的上下电压边界; 以及基于所述上下电压边界确定所述一个或多个DFE锁存器的阈值位置。 比较可以可选地包括获得由至少一个决定锁存器和至少一个漫游锁存器获得的样本的异或（XOR）。 XOR比较将零点击数的单面数据眼的开口位置
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5.发明授权Methods and apparatus for detecting a loss of lock condition in a clock and data recovery system 有权用于检测时钟和数据恢复系统中锁定状况的损失的方法和装置公开(公告)号：US08208521B2
公开(公告)日：2012-06-26
申请号：US11967632
申请日：2007-12-31
IPC分类号： H04B17/00
CPC分类号： H04L7/0062 , H04L7/0083
摘要： Methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. A loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions. Generally, the predefined conditions identify a loss of the data eye (e.g., when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected.
摘要翻译： 提供了用于检测时钟和数据恢复系统中的锁定状况的损失的方法和装置。 在时钟和数据恢复系统中检测到锁定状态的损失，该系统通过使用由恢复时钟计时的一个或多个锁存器对接收到的信号进行多个不同相位的采样来产生来自接收信号的恢复时钟信号; 评估样本以监测与接收信号相关联的数据眼; 并且如果数据眼不满足一个或多个预定条件，则检测锁定条件的损失。 通常，预定义的条件识别数据眼睛的损失（例如，当不能基本上检测到数据眼时），例如，基于数据眼睛的打开程度。 如果检测到锁定状态的丢失，则可以重新启动时钟和数据恢复系统。
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6.发明授权Method and apparatus for decision-feedback equalization using single-sided eye with global minimum convergence 有权使用具有全局最小收敛的单面眼的判决反馈均衡的方法和装置公开(公告)号：US07720142B2
公开(公告)日：2010-05-18
申请号：US11686148
申请日：2007-03-14
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： Methods and apparatus are provided for decision-feedback equalization with global minimum convergence. A threshold position of one or more DFE latches employed by a decision-feedback equalizer is determined by obtaining a plurality of samples of a single-sided data eye using at least one decision latch and at least one roaming latch; comparing the samples obtained by the at least one decision latch and at least one roaming latch to identify an upper and lower voltage boundary of the single-sided data eye; and determining a threshold position of the one or more DFE latches based on the upper and lower voltage boundaries. The comparison can optionally comprise obtaining an exclusive or (XOR) of the samples obtained by the at least one decision latch and at least one roaming latch. The XOR comparison positions an opening for the single-sided data eye at a zero hit count.
摘要翻译： 提供了用于具有全局最小收敛的判决反馈均衡的方法和装置。 通过使用至少一个判定锁存器和至少一个漫游锁存器获得单面数据眼睛的多个采样来确定由判决反馈均衡器采用的一个或多个DFE锁存器的阈值位置; 将由所述至少一个判定锁存器获得的样本和至少一个漫游锁存器进行比较，以识别所述单侧数据眼睛的上下电压边界; 以及基于所述上下电压边界确定所述一个或多个DFE锁存器的阈值位置。 比较可以可选地包括获得由至少一个决定锁存器和至少一个漫游锁存器获得的样本的异或（XOR）。 XOR比较将零点击数的单面数据眼的开口位置。
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