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公开(公告)号：US08432959B2
公开(公告)日：2013-04-30
申请号：US11930814
申请日：2007-10-31
CPC分类号： H04L25/0262 , H04L25/03006 , H04L25/03057 , H04L2025/03375 , H04L2025/03535 , H04L2025/03726
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.
摘要翻译： 提供了用于均衡接收信号的方法和装置。 通过更新一个或多个均衡参数来使接收信号相等; 以及如果在均衡步骤期间检测到一个或多个预定义的限定条件，则丢弃所述更新的均衡参数。 如果在平衡步骤期间未检测到预定义的限定条件，则可以使用更新的均衡参数来选择性地均衡所接收的信号。 如果在均衡步骤期间未检测到一个或多个预定义限定条件，则可以可选地存储更新的均衡参数。
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2.发明授权Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data 有权用于使用DFE检测数据为判决反馈均衡器生成一个或多个时钟信号的方法和装置公开(公告)号：US07616686B2
公开(公告)日：2009-11-10
申请号：US11356691
申请日：2006-02-17
申请人： Pervez M. Aziz , Gregory W. Sheets , Lane A. Smith
发明人： Pervez M. Aziz , Gregory W. Sheets , Lane A. Smith
IPC分类号： H03H7/30
CPC分类号： H04L7/0062 , H04L7/033 , H04L7/04 , H04L2025/0349
摘要： Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.
摘要翻译： 提供了用于使用DFE检测数据为判决反馈均衡器生成一个或多个时钟信号的方法和装置。 使用数据时钟和转换时钟对接收到的信号进行采样，以分别产生数据采样信号和转换采样信号。 为每个数据采样和转换采样信号获得DFE校正，以产生DFE检测数据和DFE转换数据。 DFE检测数据和DFE转换数据然后被施加到产生信号以调整数据时钟和转换时钟中的一个或多个的相位的相位检测器。 在多级实现中，使用与每个级别相关联的时钟对接收到的信号进行采样，并且使用垂直限幅技术来锁存样本以生成与每个所述级别相关联的DFE数据。
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公开(公告)号：US20090110046A1
公开(公告)日：2009-04-30
申请号：US11930814
申请日：2007-10-31
IPC分类号： H03K5/159
CPC分类号： H04L25/0262 , H04L25/03006 , H04L25/03057 , H04L2025/03375 , H04L2025/03535 , H04L2025/03726
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step
摘要翻译： 提供了用于均衡接收信号的方法和装置。 通过更新一个或多个均衡参数来使接收信号相等; 以及如果在均衡步骤期间检测到一个或多个预定义的限定条件，则丢弃所述更新的均衡参数。 如果在平衡步骤期间未检测到预定义的限定条件，则可以使用更新的均衡参数来选择性地均衡所接收的信号。 如果在均衡步骤期间未检测到一个或多个预定义限定条件，则可以可选地存储更新的均衡参数
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公开(公告)号：US20090110045A1
公开(公告)日：2009-04-30
申请号：US11930780
申请日：2007-10-31
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided fox equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译： 提供了均衡接收信号的方法和装置。 接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。 均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或 都）。
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5.发明申请Methods and Apparatus for Improved Jitter Tolerance in an SFP Limit Amplified Signal 失效用于改善SFP限幅放大信号中抖动容限的方法和装置公开(公告)号：US20090168940A1
公开(公告)日：2009-07-02
申请号：US11967602
申请日：2007-12-31
申请人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
发明人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
IPC分类号： H04L7/00
CPC分类号： H04B10/6972
摘要： Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要翻译： 提供了用于改善SFP限幅放大信号中的抖动容限的方法和装置。 在通信接收机中通过将接收到的信号施加到SFP限幅放大器来提高抖动容差; 并将SFP限幅放大器的输出施加到低通滤波器以提高抖动容限。 低通滤波器可选择地将可编程量的衰减应用于输出的高频分量。 低通滤波器转换速率控制（即旋转）接收信号的数据眼表示，以沿着时间轴增加数据眼睛表示。 可以通过将低通滤波器的输出施加到全通滤波器来可选地改善接收信号的噪声容限。 压摆率控制器可以评估数据眼统计量，以确定低通滤波器的设置。
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6.发明授权Methods and apparatus for improved jitter tolerance in an SFP limit amplified signal 失效用于改善SFP限幅放大信号中抖动容限的方法和装置公开(公告)号：US08040984B2
公开(公告)日：2011-10-18
申请号：US11967602
申请日：2007-12-31
申请人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
发明人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
CPC分类号： H04B10/6972
摘要： Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要翻译： 提供了用于改善SFP限幅放大信号中的抖动容限的方法和装置。 在通信接收机中通过将接收到的信号施加到SFP限幅放大器来提高抖动容差; 并将SFP限幅放大器的输出施加到低通滤波器以提高抖动容限。 低通滤波器可选择地将可编程量的衰减应用于输出的高频分量。 低通滤波器转换速率控制（即旋转）接收信号的数据眼表示，以沿着时间轴增加数据眼睛表示。 可以通过将低通滤波器的输出施加到全通滤波器来可选地改善接收信号的噪声容限。 压摆率控制器可以评估数据眼统计量，以确定低通滤波器的设置。
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7.发明授权Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量公开(公告)号：US08416907B2
公开(公告)日：2013-04-09
申请号：US12846390
申请日：2010-07-29
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
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公开(公告)号：US08027409B2
公开(公告)日：2011-09-27
申请号：US11962409
申请日：2007-12-21
IPC分类号： H03K9/00
CPC分类号： H04L25/03057 , H03K5/135 , H03M9/00
摘要： In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.
摘要翻译： 在示例性实施例中，关于经由符号间干扰（ISI）噪声的SERDES（串行器/解串行器）背板主信道和来自其他信道的增加的串扰噪声来描述基于噪声预测的数据检测。 基于噪声预测的数据检测将来自符号间干扰（ISI）噪声的附加误差分量和来自串扰噪声的附加误差分量组合成总体噪声预测误差项，并消除各种组件的残留ISI和串扰的影响 的示例性实施例。
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9.发明授权Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量公开(公告)号：US07792234B2
公开(公告)日：2010-09-07
申请号：US11414521
申请日：2006-04-28
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
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10.发明申请METHOD AND APPARATUS FOR INTEGRAL STATE INITIALIZATION AND QUALITY OF LOCK MONITORING IN A CLOCK AND DATA RECOVERY SYSTEM 有权综合状态初始化和时钟和数据恢复系统中的监控质量的方法与装置公开(公告)号：US20100290513A1
公开(公告)日：2010-11-18
申请号：US12846390
申请日：2010-07-29
IPC分类号： H04B17/00
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
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