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1.发明申请公开(公告)号：US20130226536A1
公开(公告)日：2013-08-29
申请号：US13406897
申请日：2012-02-28
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.
摘要翻译： 公开了一种方法，其包括使用在计算机化设备上运行的电路识别引擎来检测集成电路中的数量和类型设备。 该方法通过选择一组主导有源器件并使用该主导有源器件集来执行仿真来表征器件变化。 可以使用三种不同的选项来优化任何电弧/压摆/负载组合的模拟次数。 积极减少使用最少数量的模拟，以牺牲一些精度损失为代价，保守的减少可以减少精确度损失可忽略的模拟次数，动态减少动态地确定给定精度要求所需的最小模拟次数。
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2.发明授权公开(公告)号：US09323875B2
公开(公告)日：2016-04-26
申请号：US13406897
申请日：2012-02-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.
摘要翻译： 公开了一种方法，其包括使用在计算机化设备上运行的电路识别引擎来检测集成电路中的设备的数量和类型。 该方法通过选择一组主导有源器件并使用该主导有源器件集来执行仿真来表征器件变化。 可以使用三种不同的选项来优化任何电弧/压摆/负载组合的模拟次数。 积极减少使用最少数量的模拟，以牺牲一些精度损失为代价，保守的减少可以减少精确度损失可忽略的模拟次数，动态减少动态地确定给定精度要求所需的最小模拟次数。
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公开(公告)号：US07275226B2
公开(公告)日：2007-09-25
申请号：US10709205
申请日：2004-04-21
CPC分类号： G06F17/5081
摘要： A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number of neighboring cells which must be explored. In every fourth iteration of the expansion process, corner cells may not be expanded. Reachable areas outside of conductors can also be explored.
摘要翻译： 一种对集成电路（IC）设计进行闩锁检查的方法，其包括使用蜂窝算法对导体区域形状进行光栅化并且接触形状并且迭代地扩展导体区域形状内的接触形状。 接触细胞的方向值可用于限制必须探索的相邻细胞的数量。 在扩展过程的第四次迭代中，角细胞可能不会扩展。 还可以探索导体之外的可达到的区域。
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4.发明申请ANALYSIS TECHNIQUES TO REDUCE SIMULATIONS TO CHARACTERIZE THE EFFECT OF VARIATIONS IN TRANSISTOR CIRCUITS 审中-公开分析技术减少模拟以表征变化对晶体管电路的影响公开(公告)号：US20080126061A1
公开(公告)日：2008-05-29
申请号：US11464014
申请日：2006-08-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Embodiments of the invention provide a method, computer program product, etc. for analysis techniques to reduce simulations to characterize the effect of variations in transistor circuits. A method of simulating transistors in an integrated circuit begins by reducing a group of parallel transistors to a single equivalent transistor. The equivalent transistor is subsequently simulated, wherein only a portion of the parallel transistors are simulated. Next, the integrated circuit is divided into channel-connected components and simulated for the channel-connected components. A table is created for each type of channel-connected component; and parameterized across chip variation equations are calculated from results of the integrated circuit simulation. Moreover, table entries are created, which include a number of transistor types, a number of unique transistor primitive patterns, and/or a number of paths through each of the transistor primitive patterns.
摘要翻译： 本发明的实施例提供了用于分析技术的方法，计算机程序产品等，以减少模拟以表征晶体管电路中的变化的影响。 在集成电路中模拟晶体管的方法通过将一组并联晶体管减少到单个等效晶体管来开始。 随后模拟等效晶体管，其中仅模拟一部分并联晶体管。 接下来，将集成电路分为通道连接部件，并对通道连接部件进行仿真。 为每种类型的通道连接组件创建一个表格; 并且通过集成电路仿真的结果计算跨芯片变化方程的参数化。 此外，创建表条目，其包括多个晶体管类型，多个独特的晶体管原始图案和/或通过晶体管基元图案中的每一个的路径的数量。
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