公开(公告)号：US11077050B2

公开(公告)日：2021-08-03

申请号：US16496182

申请日：2018-03-19

申请人： MERCK SHARP & DOHME CORP. ,  MERCK SHARP & DOHME B. V. ,  Sachin Mittal ,  Irina Kazakevich ,  Himanshu Bhattacharjee ,  Peter Bakker ,  Luke Schenck ,  David J. Goldfarb ,  Amitava Mitra ,  Donna Carroll ,  Nazia Khawaja

发明人： Sachin Mittal ,  Irina Kazakevich ,  Himanshu Bhattacharjee ,  Peter Bakker ,  Luke Schenck ,  David J. Goldfarb ,  Amitava Mitra ,  Donna Carroll ,  Nazia Khawaja

IPC分类号： A61K31/4439 ,  A61K9/00 ,  A61K47/10 ,  A61K47/22 ,  A61K47/26 ,  A61K47/38 ,  A61K9/10

摘要： The instant invention provides pharmaceutical formulations for a long acting injectable drug product comprising a suspension of doravirine for parenteral administration via intramuscular or subcutaneous routes. The drug product can be used for the treatment or prophylaxis of infection by HIV or for the treatment, prophylaxis, or delay in the onset of AIDS (acquired immunodeficiency syndrome) or ARC (AIDS related complex).

公开(公告)号：US06501308B2

公开(公告)日：2002-12-31

申请号：US09972217

申请日：2001-10-05

申请人： Peter Bakker ,  Fred S. Rennig

发明人： Peter Bakker ,  Fred S. Rennig

IPC分类号： H03L706

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/06

摘要： The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time. This circuit component (62) is controlled in such a way as to change the signal transit time in inverse proportion to the changes of the output signals of the clock generator (16).

公开(公告)号：US4570528A

公开(公告)日：1986-02-18

申请号：US504487

申请日：1983-06-15

申请人： Peter Bakker

发明人： Peter Bakker

IPC分类号： F16F7/00 ,  G10C3/14 ,  G10K1/30 ,  G10C3/12

CPC分类号： F16F7/00 ,  G10C3/14 ,  G10K1/30

摘要： In a carillon or chimes keyboard, which may be a manual or a pedal set, theeys (sticks or pedals) and the frame for taking them up pivotally are provided with cooperating surfaces, one surface on the key hitting the other surface on the frame at the end of the upward release movement of the key after it has been depressed for operating a bell.For dampening the clattering noise caused by this hitting, the invention provides for such cooperating surfaces on the keys and the frame, which are inclined, preferably at about 30.degree., to the upward direction of movement of the keys just before they hit on the frame during this release movement.

摘要翻译： 在可以是手动或踏板的钟琴或钟琴键盘中，键（杆或踏板）和用于将它们上升的框架枢转地设置有协作表面，键上的一个表面击中框架上的另一个表面 在钥匙被按下以操作钟之后，钥匙的向上释放运动结束。 为了减轻由此撞击引起的咔嗒声，本发明提供了键和框架上的这些配合表面，其优选地在键被碰到框架之前倾斜，优选地在大约30度处与键向上移动的方向 在这个释放运动。

公开(公告)号：US20200289406A1

公开(公告)日：2020-09-17

申请号：US16496182

申请日：2018-03-19

申请人： Sachin MITTAL ,  Irina KAZAKEVICH ,  Himanshu BHATTAQCHARJEE ,  Peter BAKKER ,  Luke J. SCHENCK ,  David J. GOLDFARB ,  Amitava MITRA ,  Donna CARROLL ,  Nazia KHAWAJA ,  MERCK SHARP & DOHME CORP. ,  MERCK SHARP & DOHME B. V.

发明人： Sachin Mittal ,  Irina Kazakevich ,  Himanshu Bhattacharjee ,  Peter Bakker ,  Luke Schenck ,  David J. Goldfarb ,  Amitava Mitra ,  Donna Carroll ,  Nazia Khawaja

IPC分类号： A61K9/00 ,  A61K31/4439 ,  A61K47/26 ,  A61K47/22 ,  A61K47/10 ,  A61K47/38

摘要： The instant invention provides pharmaceutical formulations for a long acting injectable drug product comprising a suspension of doravirine for parenteral administration via intramuscular or subcutaneous routes. The drug product can be used for the treatment or prophylaxis of infection by HIV or for the treatment, prophylaxis, or delay in the onset of AIDS (acquired immunodeficiency syndrome) or ARC (AIDS related complex).

公开(公告)号：US20100194915A1

公开(公告)日：2010-08-05

申请号：US12678197

申请日：2008-01-09

申请人： Peter Bakker ,  Johan Schirris

发明人： Peter Bakker ,  Johan Schirris

IPC分类号： H04N9/73

CPC分类号： H04N9/045 ,  G06T3/4015 ,  G06T2200/28 ,  H04N2209/046

摘要： In a method suitable for processing colour values provided by a camera sensor comprising pixels of different colours, values of a first colour at positions of pixels of a second and a third colour are interpolated (102) based on an averaging using at least one control value.

摘要翻译： 在适于处理由包括不同颜色的像素的相机传感器提供的颜色值的方法中，基于使用至少一个控制值的平均来内插（102）第二颜色和第三颜色的像素的位置处的第一颜色的值 。

公开(公告)号：US06940336B2

公开(公告)日：2005-09-06

申请号：US10695334

申请日：2003-10-28

申请人： Peter Bakker

发明人： Peter Bakker

IPC分类号： G05F1/575 ,  G05F1/10 ,  G05F3/02

CPC分类号： G05F1/575

摘要： Voltage regulator with an output transistor MP1, including a first PMOS FET, whereby the input voltage Vdd of the voltage regulator is applied to the source of the output transistor MP1 and where the drain of the output transistor MP1 constitutes the output of the voltage regulator. The voltage regulator, furthermore, includes a regulation circuit 1 that may, for example, consist of an error amplifier and that controls the output transistor in such a way that the least possible deviations between the output voltage Vout and the target output voltage are allowed to occur. The voltage regulator includes a switch-on protection circuit that includes a second PMOS FET MP2, whereby the source of the second PMOS FET MP2 is connected to the input voltage Vdd of the voltage regulator, the drain of the second PMOS FET MP2, by way of a pulldown resistor R3, to a reference potential Vss, and the gate of the second PMOS FET MP2 to the reference potential Vss, and which furthermore includes a third PMOS FET MP3, where the source of the third PMOS FET MP3 is connected to the input voltage Vdd of the voltage regulator, the drain of the third PMOS FET MP3 is connected to the gate of the output transistor MP1, and the gate of the third PMOS FET MP3 is connected to the drain of the second PMOS FET MP2.

摘要翻译： 具有输出晶体管MP 1的电压调节器，包括第一PMOS FET，由此将稳压器的输入电压Vdd施加到输出晶体管MP 1的源极，并且其中输出晶体管MP 1的漏极构成 电压调节器。 此外，电压调节器包括调节电路1，其可以例如由误差放大器组成并且以这样的方式控制输出晶体管，使得输出电压Vout和目标输出电压之间的最小偏差被允许 发生。 电压调节器包括接通保护电路，其包括第二PMOS FET MP 2，由此第二PMOS FET MP 2的源极连接到电压调节器的输入电压Vdd，第二PMOS FET MP 2的漏极 通过下拉电阻器R 3到参考电位Vss以及第二PMOS FET MP2的栅极到参考电位Vss，并且还包括第三PMOS FET MP 3，其中第三PMOS FET FET MP 3连接到电压调节器的输入电压Vdd，第三PMOS FET MP 3的漏极连接到输出晶体管MP1的栅极，并且第三PMOS FET MP 3的栅极连接到 第二PMOS FET MP 2的漏极。