公开(公告)号：US06665218B2

公开(公告)日：2003-12-16

申请号：US10007603

申请日：2001-12-05

申请人： Peter J. Meier ,  Gerald L Esch, Jr.

发明人： Peter J. Meier ,  Gerald L Esch, Jr.

IPC分类号： G11C700

CPC分类号： H03L7/0812 ,  H04L7/0337

摘要： A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.

摘要翻译： 自校准寄存器。 在代表性实施例中，公开了通过抵消系统不匹配的固有系统源来增加源同步输入/输出（I / O）数据速率的寄存器。 位线路径和器件之间的系统不匹配的系统来源，例如印刷电路板路径长度，封装迹线长度，片上时钟路由，时钟偏移，器件导通电压等相对于 参考时钟信号由数据信号的编程延迟。 适当的延迟通过相移检测电路获得，然后由控制电路施加到信号延迟电路。

公开(公告)号：US07010641B2

公开(公告)日：2006-03-07

申请号：US10355775

申请日：2003-01-31

申请人： Gerald L Esch, Jr. ,  Richard S. Rodgers

发明人： Gerald L Esch, Jr. ,  Richard S. Rodgers

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F17/00

CPC分类号： G06F17/5077

摘要： A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within the same routing track parallel to the closest portion of a primary bus route. All other blocks, termed secondary blocks, have ports that are positioned so that no two ports of any secondary block reside within the same routing track perpendicular to the closest portion of the primary bus route. A primary connection for each signal of the signal bus is then placed over each port of the primary block substantially along the length of the primary route. Each port of each secondary block then has a secondary track connecting it in a perpendicular fashion to the proper primary track.

摘要翻译： 提供一种路由集成电路信号总线的方法。 选择具有要连接到信号总线的端口的一组块中的一个作为主块，其端口被定位成使得该块的两个端口不在与最接近的部分的最近部分平行的同一路由轨道内 一条主要巴士路线。 称为次级块的所有其他块具有定位的端口，使得任何次级块的两个端口不位于与主总线路由的最近部分垂直的相同路由轨道内。 然后，基本上沿着主要路线的长度，将信号总线的每个信号的主要连接放置在主块的每个端口上。 然后，每个次级块的每个端口具有将其以与正确的主轨道垂直的方式连接的次级轨道。

公开(公告)号：US06268750B1

公开(公告)日：2001-07-31

申请号：US09481467

申请日：2000-01-11

申请人： Gerald L Esch, Jr.

发明人： Gerald L Esch, Jr.

IPC分类号： H03H1126

CPC分类号： H03H11/28

摘要： A method and circuit for flattening the output resistance response on a signal pad of an integrated circuit is presented. Impedance matching is accomplished using pull-up and pull-down FET arrays. Various combinations of pull-up PFETs in the pull-up FET array are programmably enabled by a pull-up calibration word when driving the output pad high. Various combinations of pull-down NFETs in the pull-down FET array are programmably enabled by a pull-down calibration word when driving the output pad low. An NFET in the pull-up FET calibration array and a PFET in the pull-down FET array respectively allow the output driver to supply more current during the initial stages of a voltage transition, resulting in a flatter overall output resistance Ro response.

摘要翻译： 提出了一种用于在集成电路的信号焊盘上平坦化输出电阻响应的方法和电路。 使用上拉和下拉FET阵列实现阻抗匹配。 上拉FET阵列中的上拉PFET的各种组合可以通过上拉校准字在驱动输出焊盘高时可编程地使能。 下拉式FET阵列中的下拉式NFET的各种组合可以通过下拉校准字在驱动输出焊盘时可编程地使能。 上拉FET校准阵列中的NFET和下拉FET阵列中的PFET分别允许输出驱动器在电压转换的初始阶段期间提供更多的电流，导致更平坦的整体输出电阻Ro响应。