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1.发明授权System and method for adapting an analog echo canceller in a transceiver front end 有权在收发器前端适配模拟回波消除器的系统和方法公开(公告)号：US06980644B1
公开(公告)日：2005-12-27
申请号：US09570078
申请日：2000-05-12
CPC分类号： H04M9/082
摘要： There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.
摘要翻译： 公开了一种用于全双工收发器的回波消除器电路，其包括能够通过电缆发送模拟发射信号的线路驱动器并且包括能够从电缆接收模拟接收信号的线路接收器的线路接收机。 回波消除器阻抗模型电路耦合到线路驱动器的输出端并耦合到线路接收机的输入。 回波消除器阻抗模型电路产生质量相等并且与表示模拟接收信号中存在的信号回波的电流相位相反的回波消除器电流。 回波消除器阻抗模型电路具有用于产生回波消除器电流的可变阻抗。 可变阻抗具有至少一个可变电阻器和至少一个可变电容器。 回波消除器阻抗模型电路中的电阻和电容值响应于来自回波消除器控制电路的控制信号而变化，以补偿和消除信号回波。
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2.发明授权公开(公告)号：US07526053B1
公开(公告)日：2009-04-28
申请号：US11517435
申请日：2006-09-08
申请人： Peter J. Sallaway , Sreen Raghavan
发明人： Peter J. Sallaway , Sreen Raghavan
CPC分类号： H04L25/03267 , H04B3/23 , H04B3/32 , H04L25/03197 , H04L25/4919 , H04L2025/03363 , H04L2025/0349
摘要： A sequence detector (1400-w) operating generally according to the Viterbi algorithm contains a branch metric generator (1402-w), comparison circuitry (1403-w), and symbol generation circuitry (1404, 1405, and 1406) for converting digital values of a detector input signal into a sequence of predefined symbols chosen from an alphabet of predefined symbols. The comparison circuitry provides soft output signals for correcting errors. The soft output signals include best and second-best state metrics (pk,w(i) and p2k,w(i)) and corresponding best and second-best comparison results (Dk,w(i) and D2k,w(i)). The symbol generation circuitry typically utilizes the best comparison results to generate a preliminary sequence of the predefined symbols, checks for error in the preliminary sequence, and utilizes the second-best comparison results in correcting any such error in the preliminary sequence so as to convert it into a final sequence of the predefined symbols.
摘要翻译： 通常根据维特比算法运行的序列检测器（1400-w）包含用于转换数字值的分支度量发生器（1402-w），比较电路（1403-w）和符号生成电路（1404,1405和1406） 检测器输入信号转换成从预定符号的字母表中选择的预定符号序列。 比较电路提供用于校正错误的软输出信号。 软输出信号包括最佳和最佳状态度量（pk，w（i）和p2k，w（i））和相应的最佳和第二最佳比较结果（Dk，w（i）和D2k，w（i） ）。 符号生成电路通常利用最佳比较结果来产生预定义符号的初步序列，检查初步序列中的错误，并利用第二好的比较结果校正初步序列中的任何这样的误差，以便将其转换 进入预定义符号的最后序列。
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3.发明授权System and method for adapting an analog echo canceller in a transceiver front end 有权在收发器前端适配模拟回波消除器的系统和方法公开(公告)号：US07333603B1
公开(公告)日：2008-02-19
申请号：US11320520
申请日：2005-12-27
CPC分类号： H04M9/082
摘要： There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.
摘要翻译： 公开了一种用于全双工收发器的回波消除器电路，其包括能够通过电缆发送模拟发射信号的线路驱动器并且包括能够从电缆接收模拟接收信号的线路接收器的线路接收机。 回波消除器阻抗模型电路耦合到线路驱动器的输出端并耦合到线路接收机的输入。 回波消除器阻抗模型电路产生质量相等并且与表示模拟接收信号中存在的信号回波的电流相位相反的回波消除器电流。 回波消除器阻抗模型电路具有用于产生回波消除器电流的可变阻抗。 可变阻抗具有至少一个可变电阻器和至少一个可变电容器。 回波消除器阻抗模型电路中的电阻和电容值响应于来自回波消除器控制电路的控制信号而变化，以补偿和消除信号回波。
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公开(公告)号：US07050517B1
公开(公告)日：2006-05-23
申请号：US09560109
申请日：2000-04-28
申请人： Peter J. Sallaway , Sreen Raghavan
发明人： Peter J. Sallaway , Sreen Raghavan
IPC分类号： H04B1/10
CPC分类号： H04L25/03267 , H04B3/23 , H04B3/32 , H04L25/03197 , H04L25/4919 , H04L2025/03363 , H04L2025/0349
摘要： A detector system for high-speed Ethernet LAN is described. One embodiment includes a detector system having N one dimensional sequence detector equalizers in combination with an N-dimensional traceback decoder. The detector system detects N-dimensional symbols transmitted over N separate transport channels to N one-dimensional receivers. In one embodiment, Gigabit Ethernet receiver includes a four-wire transport to four 1D receivers and a 4D detector. The 4D detector in one embodiment is a parity code detector. In another embodiment, the 4D detector is a 4D trellis code detector.
摘要翻译： 描述了用于高速以太网LAN的检测器系统。 一个实施例包括具有N个一维序列检测器均衡器和N维回溯解码器的检测器系统。 检测器系统检测通过N个分离的传输信道发送到N个一维接收机的N维符号。 在一个实施例中，千兆以太网接收器包括四线传输到四个1D接收机和4D检测器。 一个实施例中的4D检测器是奇偶校验码检测器。 在另一个实施例中，4D检测器是4D格状码检测器。
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公开(公告)号：US08787430B2
公开(公告)日：2014-07-22
申请号：US12558781
申请日：2009-09-14
CPC分类号： H04L27/2601
摘要： A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.
摘要翻译： 公开了允许组件之间数据高数据速率传输的通信系统。 在传输介质上以K个频率分离的信道发送N位并行数据，以充分利用传输介质的总带宽。 因此，可以在单个通道上进行低数据位传输来实现非常高的数据速率传输。 为通信系统描述了发射机系统和接收机系统。
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6.发明授权Sequence detector using Viterbi algorithm with reduced complexity sequence detection via state reduction using symbol families 有权使用Viterbi算法的序列检测器，通过使用符号族的状态减少来降低复杂度序列检测公开(公告)号：US07443936B1
公开(公告)日：2008-10-28
申请号：US11431451
申请日：2006-05-09
申请人： Peter J. Sallaway , Sreen Raghavan
发明人： Peter J. Sallaway , Sreen Raghavan
CPC分类号： H04L25/03267 , H04B3/23 , H04B3/32 , H04L25/03197 , H04L25/4919 , H04L2025/03363 , H04L2025/0349
摘要： A sequence detector (1600-w) operating generally according to the Viterbi algorithm uses state reduction via division into symbol families to reduce the complexity of sequence detection. The sequence detector contains a branch metric generator (1402-w), comparison circuitry (1603-w), and symbol generation circuitry (1604, 1605-w, and 1606) for converting digital values of an input signal into a sequence of symbols chosen from an alphabet of predefined symbols allocated into multiple non-overlapping families each formed with a plurality of the predefined symbols. The branch metric generator makes intra-family branch selections, each of which is one of a plurality of branches respectively corresponding to a family's symbols, and generates corresponding branch metrics. The comparison circuitry determines state metrics and generates corresponding comparison results. The symbol generation circuitry utilizes the comparison results and the branch selections, or selection information generated from the branch selections, to generate the sequence of predefined symbols.
摘要翻译： 通常根据维特比算法运行的序列检测器（1600-w）通过划分成符号族来减少状态以降低序列检测的复杂度。 序列检测器包含一个分支度量发生器（1402-w），比较电路（1603-w）和符号产生电路（1604,1605-w和1606），用于将输入信号的数字值转换成所选择的符号序列 从分配给多个非重叠系列的预定符号的字母表中分别形成多个预定符号。 分支度量发生器进行族内分支选择，每个分支选择分别对应于一系列符号的多个分支之一，并产生相应的分支度量。 比较电路确定状态度量并产生相应的比较结果。 符号生成电路利用比较结果和分支选择或从分支选择生成的选择信息来生成预定符号的序列。
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7.发明授权Transceiver system with analog and digital signal echo cancellation having adaptably adjustable filter characteristics 有权具有模拟和数字信号回波消除的收发器系统具有可调节的滤波器特性公开(公告)号：US08447000B2
公开(公告)日：2013-05-21
申请号：US12319985
申请日：2009-01-12
CPC分类号： H04L25/03057 , H04L25/03254
摘要： A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.
摘要翻译： 提出了一种容易从具有长电缆长度的传输通道接收信号的接收机。 接收机包括一个模拟预滤波器，用于消除来自预定传输信道的失真和符号间干扰。 模拟预滤波器与提供数字均衡的数字接收机耦合。 模拟均衡与数字均衡的组合允许简化的数字均衡，同时保持数字信号处理的通用性。
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8.发明授权Transceiver system with analog and digital signal echo cancellation having adaptably adjustable filter characteristics 有权具有模拟和数字信号回波消除的收发器系统具有可调节的滤波器特性公开(公告)号：US07756228B1
公开(公告)日：2010-07-13
申请号：US11542532
申请日：2006-10-02
CPC分类号： H04L25/03057 , H04L25/03254
摘要： Analog echo-cancelling circuitry (611 and 627) operates on an input analog signal that includes an echo of an output signal, or on an analog signal generated from the input signal, to produce an analog signal with reduced echo. An analog-to-digital converter (210) converts the echo-reduced analog signal, or an analog signal generated therefrom, into a digital signal. Digital echo-cancelling circuitry (615 and 621) operates on the digital signal, or on a digital signal generated therefrom, to produce a digital signal with further reduced echo. An output decoder (605) decodes the echo-reduced digital signal, or a digital signal generated therefrom, into a stream of symbols. The echo-filtering characteristics of both echo-cancelling circuitries are typically adaptively adjusted during generation of the symbol stream. The analog echo-filtering characteristics may be adapted in response to information provided by operating on the echo-reduced digital signal or on a digital signal generated therefrom.
摘要翻译： 模拟回波消除电路（611和627）对包括输出信号的回波或输入信号产生的模拟信号的输入模拟信号进行操作，以产生具有降低回波的模拟信号。 模数转换器（210）将回波减小的模拟信号或由其产生的模拟信号转换为数字信号。 数字回波消除电路（615和621）对数字信号或由其产生的数字信号进行操作以产生具有进一步降低的回波的数字信号。 输出解码器（605）将回波减小的数字信号或由其产生的数字信号解码成符号流。 两个回波消除电路的回波滤波特性通常在符号流生成期间进行自适应调整。 模拟回波滤波特性可以响应于通过对回波减小的数字信号或由其产生的数字信号进行操作而提供的信息而被适配。
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公开(公告)号：US07590168B2
公开(公告)日：2009-09-15
申请号：US09965242
申请日：2001-09-26
CPC分类号： H04L27/2601
摘要： A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.
摘要翻译： 公开了允许组件之间数据高数据速率传输的通信系统。 在传输介质上以K个频率分离的信道发送N位并行数据，以充分利用传输介质的总带宽。 因此，可以在单个通道上进行低数据位传输来实现非常高的数据速率传输。 为通信系统描述了发射机系统和接收机系统。
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公开(公告)号：US07254198B1
公开(公告)日：2007-08-07
申请号：US09561086
申请日：2000-04-28
IPC分类号： H04B1/10
CPC分类号： H04L25/03057 , H04L25/03254
摘要： A receiver system suitable for a local area network contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605). A symbol-information-carrying input analog signal (yk), or a first intermediate analog signal generated from the input analog signal, is filtered by filtering circuitry in the pre-filter to produce a filtered analog signal (Zs) with reduced intersymbol interference. The filtering circuitry operates according to a transfer function such as (b1s+1)/(a2s2+a1s+1) or (1−Vc)+VcPF(s) where Vc is adaptively varied. The analog-to-digital converter provides analog-to-digital signal conversion. The equalizer provides digital signal equalization to produce an equalized digital signal (a′k) as a stream of equalized digital values. The decoder converts the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols.
摘要翻译： 适用于局域网的接收机系统包含模拟预滤波器（207或619），模拟 - 数字转换器（210），数字均衡器（212）和解码器（605）。 由输入的模拟信号产生的符号信息输入模拟信号（或从输入的模拟信号产生的第一中间模拟信号）由预滤波器中的滤波电路进行滤波，以产生经滤波的模拟信号 （Z s S）具有减少的符号间干扰。 滤波电路根据传递函数进行操作，例如（b 1> 1 + 1）/（a 2＆lt; 2＆gt; 2＆lt; 1 + 1）或（1-V C c）+ V C c C（s）其中V C c C被自适应地变化 。 模数转换器提供模数转换。 均衡器提供数字信号均衡以产生均衡的数字信号（一个“k”）作为均衡数字值的流。 解码器将均衡的数字值或从均衡的数字值生成的中间数字值转换成符号流。
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