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1.发明申请Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits 有权用于高密度和高性能集成电路的互补金属氧化物半导体晶体管结构公开(公告)号：US20070181947A1
公开(公告)日：2007-08-09
申请号：US11347164
申请日：2006-02-03
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , B82Y10/00 , B82Y40/00 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/775
摘要： A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.
摘要翻译： 半导体器件可以包括衬底和形成在衬底上的绝缘层。 可以在绝缘层上形成多层鳍，并且可以包括在垂直方向上被绝缘层隔离的两个半导体层。 包括第一源极区域，第一沟道区域和第一漏极区域的第一MOS型器件被布置在多层鳍片的第一半导体层上。 包括第二源极区，第二沟道区和第二漏极区的第二MOS型器件布置在多层鳍中的第二半导体层上。 栅电极设置成与第一和第二沟道区垂直相邻。
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2.发明授权Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits 有权用于高密度和高性能集成电路的互补金属氧化物半导体晶体管结构公开(公告)号：US07545008B2
公开(公告)日：2009-06-09
申请号：US11347164
申请日：2006-02-03
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , B82Y10/00 , B82Y40/00 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/775
摘要： A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.
摘要翻译： 半导体器件可以包括衬底和形成在衬底上的绝缘层。 可以在绝缘层上形成多层鳍，并且可以包括在垂直方向上被绝缘层隔离的两个半导体层。 包括第一源极区域，第一沟道区域和第一漏极区域的第一MOS型器件被布置在多层鳍片的第一半导体层上。 包括第二源极区，第二沟道区和第二漏极区的第二MOS型器件布置在多层鳍中的第二半导体层上。 栅电极设置成与第一和第二沟道区垂直相邻。
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