公开(公告)号：US07663635B2

公开(公告)日：2010-02-16

申请号：US11139917

申请日：2005-05-27

申请人： Philip J. Rogers ,  Jeffrey Gongxian Cheng ,  Dmitry Semiannikov ,  Raja Koduri

发明人： Philip J. Rogers ,  Jeffrey Gongxian Cheng ,  Dmitry Semiannikov ,  Raja Koduri

IPC分类号： G06F12/10 ,  G06F15/16

CPC分类号： G06T1/20

摘要： A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics aperture relocation table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. Thus, unique addresses need not be generated for each VPU.

摘要翻译： 描述了在多视频处理器（多VPU）系统中的存储器映射的系统和方法。 在各种实施例中，并行地在多个VPU之间共享呈现任务，以最小的成本提供改善的性能和能力。 在各种实施例中，系统中的多个VPU访问彼此的本地存储器以促进协作视频处理。 在一个实施例中，系统中的每个VPU具有映射到其自己的图形孔径重定位表（GART）表的彼此VPU的本地存储器，以便于经由虚拟寻址方案的访问。 每个VPU使用相同的虚拟地址来映射到其他VPU本地存储器。 这允许驱动程序向每个VPU发送完全相同的写入命令，包括用于诸如编写渲染数据的操作的目标地址的数值。 因此，不需要为每个VPU生成唯一的地址。

公开(公告)号：US20060267990A1

公开(公告)日：2006-11-30

申请号：US11139917

申请日：2005-05-27

申请人： Philip Rogers ,  Jeffrey Cheng ,  Dmitry Semiannikov ,  Raja Koduri

发明人： Philip Rogers ,  Jeffrey Cheng ,  Dmitry Semiannikov ,  Raja Koduri

IPC分类号： G06F15/16

CPC分类号： G06T1/20

摘要： A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics aperture relocation table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. Thus, unique addresses need not be generated for each VPU.

摘要翻译： 描述了在多视频处理器（多VPU）系统中的存储器映射的系统和方法。 在各种实施例中，并行地在多个VPU之间共享呈现任务，以最小的成本提供改善的性能和能力。 在各种实施例中，系统中的多个VPU访问彼此的本地存储器以促进协作视频处理。 在一个实施例中，系统中的每个VPU具有映射到其自己的图形孔径重定位表（GART）表的彼此VPU的本地存储器，以便于经由虚拟寻址方案的访问。 每个VPU使用相同的虚拟地址来映射到其他VPU本地存储器。 这允许驱动程序向每个VPU发送完全相同的写入命令，包括用于诸如编写渲染数据的操作的目标地址的数值。 因此，不需要为每个VPU生成唯一的地址。

公开(公告)号：US20100188411A1

公开(公告)日：2010-07-29

申请号：US12359071

申请日：2009-01-23

申请人： Dmitry Semiannikov ,  Korhan Erenben ,  Raja Koduri

发明人： Dmitry Semiannikov ,  Korhan Erenben ,  Raja Koduri

IPC分类号： G09G5/39

CPC分类号： G09G5/001 ,  G09G5/363 ,  G09G5/39

摘要： Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc.

摘要翻译： 本文公开了用于非图形相关任务的图形存储器（也称为视频存储器）的方法和装置的实施例。 在一个实施例中，图形处理单元（GPU）包括具有硬件和软件的VRAM高速缓存模块，以提供和管理为中央处理单元（CPU）资源的附加高速缓存。 在一个实施例中，VRAM缓存模块包括向CPU注册的VRAM高速缓存驱动器，接受来自CPU的读请求，并使用VRAM缓存来服务请求。 在各种实施例中，VRAM高速缓存可配置为唯一的GPU高速缓存或备选地，作为第一级高速缓存，第二级高速缓存等

公开(公告)号：US08514233B2

公开(公告)日：2013-08-20

申请号：US12359071

申请日：2009-01-23

申请人： Dmitry Semiannikov ,  Korhan Erenben ,  Raja Koduri

发明人： Dmitry Semiannikov ,  Korhan Erenben ,  Raja Koduri

IPC分类号： G09G5/39

CPC分类号： G09G5/001 ,  G09G5/363 ,  G09G5/39

摘要： Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc.

摘要翻译： 本文公开了用于非图形相关任务的图形存储器（也称为视频存储器）的方法和装置的实施例。 在一个实施例中，图形处理单元（GPU）包括具有硬件和软件的VRAM高速缓存模块，以提供和管理为中央处理单元（CPU）资源的附加高速缓存。 在一个实施例中，VRAM缓存模块包括向CPU注册的VRAM高速缓存驱动器，接受来自CPU的读请求，并使用VRAM缓存来服务请求。 在各种实施例中，VRAM高速缓存可配置为唯一的GPU高速缓存或备选地，作为第一级高速缓存，第二级高速缓存等

公开(公告)号：US08137127B2

公开(公告)日：2012-03-20

申请号：US11955798

申请日：2007-12-13

申请人： James D. Hunkins ,  Lawrence J. King ,  Raja Koduri

发明人： James D. Hunkins ,  Lawrence J. King ,  Raja Koduri

IPC分类号： H01R13/00

CPC分类号： H01R12/7082 ,  H01R12/724 ,  H01R2201/06

摘要： In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing. The electronic device housing further includes a passive or active cooling mechanism such as a fan positioned to cool the circuitry during normal operation. In one example, the electronic device does not include a host processor and instead a host processor is in a separate electronic device that communicates with the graphics processing circuitry through the divided multi connector element differential bus connector. In another example, a CPU (or one or more CPUs) is also co-located on the circuit substrate with the circuitry to provide a type of parallel host processing capability with an external device.

摘要翻译： 在一个示例中，电子设备包括包括A / C输入或DC输入的壳体，以及包括电子电路的至少一个电路基板，诸如基于A / C输入或DC输入接收功率的图形处理电路。 电子设备还包括耦合到电子电路的分开的多连接器元件差分总线连接器。 分离的多连接器元件差分总线连接器包括与电路基板连接的单个壳体，并且连接器壳体包括分开的电子接触配置，其包括由相邻的第二组镜像电触点分开的第一组电触点，其中每个 电连接组包括一排至少下部和上部触点。 在一个示例中，电子设备壳体包括适于提供空气流过壳体的空气流通道，例如格栅。 电子设备外壳还包括无源或主动冷却机构，例如风扇，其定位成在正常操作期间冷却电路。 在一个示例中，电子设备不包括主机处理器，而是主机处理器位于通过分开的多连接器元件差分总线连接器与图形处理电路通信的单独的电子设备中。 在另一示例中，CPU（或一个或多个CPU）也与电路共同位于电路基板上，以提供与外部设备的并行主机处理能力的类型。

公开(公告)号：US20090157938A1

公开(公告)日：2009-06-18

申请号：US11955798

申请日：2007-12-13

申请人： James D. Hunkins ,  Lawrence J. King ,  Raja Koduri

发明人： James D. Hunkins ,  Lawrence J. King ,  Raja Koduri

IPC分类号： G06F13/36 ,  H01R24/00

CPC分类号： H01R12/7082 ,  H01R12/724 ,  H01R2201/06

摘要： In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing. The electronic device housing further includes a passive or active cooling mechanism such as a fan positioned to cool the circuitry during normal operation. In one example, the electronic device does not include a host processor and instead a host processor is in a separate electronic device that communicates with the graphics processing circuitry through the divided multi connector element differential bus connector. In another example, a CPU (or one or more CPUs) is also co-located on the circuit substrate with the circuitry to provide a type of parallel host processing capability with an external device.

摘要翻译： 在一个示例中，电子设备包括包括A / C输入或DC输入的壳体，以及包括电子电路的至少一个电路基板，诸如基于A / C输入或DC输入接收功率的图形处理电路。 电子设备还包括耦合到电子电路的分开的多连接器元件差分总线连接器。 分离的多连接器元件差分总线连接器包括与电路基板连接的单个壳体，并且连接器壳体包括分开的电子接触配置，其包括由相邻的第二组镜像电触点分开的第一组电触点，其中每个 电连接组包括一排至少下部和上部触点。 在一个示例中，电子设备壳体包括适于提供空气流过壳体的空气流通道，例如格栅。 电子设备外壳还包括无源或主动冷却机构，例如风扇，其定位成在正常操作期间冷却电路。 在一个示例中，电子设备不包括主机处理器，而是主机处理器位于通过分开的多连接器元件差分总线连接器与图形处理电路通信的单独的电子设备中。 在另一示例中，CPU（或一个或多个CPU）也与电路共同位于电路基板上，以提供与外部设备的并行主机处理能力的类型。

公开(公告)号：US20060267993A1

公开(公告)日：2006-11-30

申请号：US11140165

申请日：2005-05-27

申请人： James Hunkins ,  Raja Koduri

发明人： James Hunkins ,  Raja Koduri

IPC分类号： G06F15/16

CPC分类号： G06F15/16 ,  G06F3/14 ,  G09G5/006 ,  G09G5/363 ,  G09G2360/06

摘要： Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

公开(公告)号：US08270476B2

公开(公告)日：2012-09-18

申请号：US12347927

申请日：2008-12-31

申请人： Michael L. Schmit ,  Raja Koduri ,  Carrell Ray Killebrew

发明人： Michael L. Schmit ,  Raja Koduri ,  Carrell Ray Killebrew

IPC分类号： H04N7/50

CPC分类号： H04N19/115 ,  H04N19/124 ,  H04N19/14 ,  H04N19/17 ,  H04N19/176 ,  H04N19/61 ,  H04N19/85

摘要： Embodiments include a codec for use in a videoconferencing or similar system includes a video encoder pipeline that has a pre-processor component that is optimized to detect faces and compress the facial video data in an optimum manner. The codec has a pre-processing step that analyzes each frame on a per macroblock basis to determine the mathematical activity level per block. The activity level calculation is used as a parameter to the bitrate control module of the encoder to control the quantization, and thus the fine grained quality of the output data. An object detection module (e.g., a face detector) is placed in the pre-processing step. The object detection data is then combined with the activity level and object detection certainty value through a combinatorial algorithm comprising a weighted average or normalized multiplication process.

摘要翻译： 实施例包括用于视频会议或类似系统的编解码器，包括视频编码器流水线，该视频编码器流水线具有被优化以便以最佳方式检测面部并压缩面部视频数据的预处理器组件。 编解码器具有预处理步骤，其基于每个宏块分析每个帧以确定每个块的数学活动水平。 活动级别计算用作编码器的比特率控制模块的参数，以控制量化，从而使输出数据的细粒度质量。 物体检测模块（例如，面部检测器）被放置在预处理步骤中。 然后通过包括加权平均或归一化乘法过程的组合算法将对象检测数据与活动级别和对象检测确定性值组合。

公开(公告)号：US08212838B2

公开(公告)日：2012-07-03

申请号：US11140156

申请日：2005-05-27

申请人： Arcot J. Preetham ,  Andrew S. Pomianowski ,  Raja Koduri

发明人： Arcot J. Preetham ,  Andrew S. Pomianowski ,  Raja Koduri

IPC分类号： G09G5/00

CPC分类号： G06T5/002 ,  G06T5/009 ,  G06T2200/12 ,  G06T2207/10016 ,  G09G5/363 ,  G09G2320/02 ,  G09G2320/0261

摘要： A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

摘要翻译： 本文描述了用于改进视频处理中的抗锯齿的系统和方法。 实施例包括系统中的多个视频处理器（VPU）。 每个VPU执行像素采样和像素中心采样（也称为多采样和超级采样）的一些组合。 每个VPU在相同的像素或像素中心执行采样，但每个VPU创建不同于其他VPU对应样本的采样。 VPU每个输出已被多采样和/或超级采样到合成器中的帧数据，该合成器合成帧数据以产生抗锯齿渲染帧。 抗锯齿渲染帧具有有效双倍的抗锯齿因子。

公开(公告)号：US08199164B2

公开(公告)日：2012-06-12

申请号：US12564471

申请日：2009-09-22

申请人： Raja Koduri ,  Gordon M. Elder ,  Jeffrey A. Golds

发明人： Raja Koduri ,  Gordon M. Elder ,  Jeffrey A. Golds

IPC分类号： G09G5/00 ,  G06F15/16 ,  G06K9/00 ,  G06K9/36 ,  G06K9/48

CPC分类号： G06T15/503 ,  G06F3/14 ,  G06T7/13 ,  G06T11/203 ,  G06T15/005 ,  G06T2210/08 ,  G06T2210/52 ,  G09G5/001 ,  G09G5/363

摘要： A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.

摘要翻译： 一种在包括第一和第二图形处理单元（GPU）的系统中执行基于多采样的抗锯齿的方法和装置，其减少了在GPU之间传送的数据量并提高了传送这些数据的效率。 第一GPU使用第一多采样模式呈现帧的第一版本，并且第二GPU使用第二多采样模式在第二GPU中呈现帧的第二版本。 第二个GPU识别帧的第二个版本中的非边缘像素。 然后，该帧的第一版本中的像素仅与尚未被识别为非边缘像素的帧的第二版本中的那些像素组合以生成组合帧。