公开(公告)号：US06794694B2

公开(公告)日：2004-09-21

申请号：US09742314

申请日：2000-12-21

申请人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

发明人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  H01L21/76838 ,  H01L23/5223 ,  H01L27/10894 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

摘要翻译： 集成电路包括其上形成有半导体器件的半导体衬底及其上，位于衬底上的第一布线层，位于第一布线层上的第二布线层和电容器。 电容器具有延伸穿过第二布线层和至少部分第一布线层的金属基电荷存储电极。 布线层具有嵌入其中的互连线。

公开(公告)号：US06559499B1

公开(公告)日：2003-05-06

申请号：US09477310

申请日：2000-01-04

申请人： Glenn B Alers ,  Philip W Diodato ,  Ruichen Liu

发明人： Glenn B Alers ,  Philip W Diodato ,  Ruichen Liu

IPC分类号： H01L27108

CPC分类号： H01L28/60 ,  H01L21/31116 ,  H01L21/3185 ,  H01L27/10814 ,  H01L27/10894

摘要： A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer. The metal for the top plate of the capacitor is then deposited over the interconnect layer. The top plate of the capacitor extends into the trench. The metal layer and barrier layer are then patterned to form the top plate of the capacitor.

摘要翻译： 公开了一种在半导体器件的互连层中制造沟槽电容器的工艺。 在该过程中，在互连层中形成至少一个互连，然后将其互相平坦化。 为了形成沟槽电容器，在互连的电介质材料中形成沟槽。 沟槽的底部与底层中的金属触点连通。 在互连层上形成阻挡层材料，并进行各向异性蚀刻，将阻挡层留在沟槽的侧壁上。 然后通过在互连层上沉积金属层形成电容器的下板。 然后对金属层进行各向异性蚀刻，去除互连层表面上的金属，并沿着沟槽周边离开金属。 然后将电容器介电层沉积在互连层上并随后被图案化。 另一层屏障材料沉积在互连层上。 然后将电容器的顶板的金属沉积在互连层上。 电容器的顶板延伸到沟槽中。 然后将金属层和阻挡层图案化以形成电容器的顶板。