公开(公告)号：US06559499B1

公开(公告)日：2003-05-06

申请号：US09477310

申请日：2000-01-04

申请人： Glenn B Alers ,  Philip W Diodato ,  Ruichen Liu

发明人： Glenn B Alers ,  Philip W Diodato ,  Ruichen Liu

IPC分类号： H01L27108

CPC分类号： H01L28/60 ,  H01L21/31116 ,  H01L21/3185 ,  H01L27/10814 ,  H01L27/10894

摘要： A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer. The metal for the top plate of the capacitor is then deposited over the interconnect layer. The top plate of the capacitor extends into the trench. The metal layer and barrier layer are then patterned to form the top plate of the capacitor.

摘要翻译： 公开了一种在半导体器件的互连层中制造沟槽电容器的工艺。 在该过程中，在互连层中形成至少一个互连，然后将其互相平坦化。 为了形成沟槽电容器，在互连的电介质材料中形成沟槽。 沟槽的底部与底层中的金属触点连通。 在互连层上形成阻挡层材料，并进行各向异性蚀刻，将阻挡层留在沟槽的侧壁上。 然后通过在互连层上沉积金属层形成电容器的下板。 然后对金属层进行各向异性蚀刻，去除互连层表面上的金属，并沿着沟槽周边离开金属。 然后将电容器介电层沉积在互连层上并随后被图案化。 另一层屏障材料沉积在互连层上。 然后将电容器的顶板的金属沉积在互连层上。 电容器的顶板延伸到沟槽中。 然后将金属层和阻挡层图案化以形成电容器的顶板。

公开(公告)号：US08030777B1

公开(公告)日：2011-10-04

申请号：US11671161

申请日：2007-02-05

申请人： Bart van Schravendijk ,  Thomas W Mountsier ,  Mahesh K Sanganeria ,  Glenn B Alers ,  Roey Shaviv

发明人： Bart van Schravendijk ,  Thomas W Mountsier ,  Mahesh K Sanganeria ,  Glenn B Alers ,  Roey Shaviv

IPC分类号： H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886

摘要： Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

摘要翻译： 在制造电子部件的方法和根据这些方法制造的电子部件的过程中保护暴露的金属镶嵌互连表面的方法。 具有暴露的金属表面的镶嵌区域的集成电路结构被提供到封闭处理室中，由此第一反应物与暴露的金属表面接触以将金属层的顶部部分转变成保护性自对准缓冲层。 使第一反应物与该金属层的金属原子反应的分子在该金属层内完全形成保护性自对准缓冲层。 或者，将表面活性反应物分子吸附到暴露的金属表面上形成保护性自对准缓冲层。 可以将第二反应物与保护性自对准缓冲层接触以在保护性自对准缓冲层上直接形成自对准电介质盖层。

公开(公告)号：US07396759B1

公开(公告)日：2008-07-08

申请号：US10980076

申请日：2004-11-03

申请人： Bart van Schravendijk ,  Thomas W Mountsier ,  Mahesh K Sanganeria ,  Glenn B Alers ,  Roey Shaviv

发明人： Bart van Schravendijk ,  Thomas W Mountsier ,  Mahesh K Sanganeria ,  Glenn B Alers ,  Roey Shaviv

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886

摘要： Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

摘要翻译： 在制造电子部件的方法和根据这些方法制造的电子部件的过程中保护暴露的金属镶嵌互连表面的方法。 具有暴露的金属表面的镶嵌区域的集成电路结构被提供到封闭处理室中，由此第一反应物与暴露的金属表面接触以将金属层的顶部部分转变成保护性自对准缓冲层。 使第一反应物与该金属层的金属原子反应的分子在该金属层内完全形成保护性自对准缓冲层。 或者，将表面活性反应物分子吸附到暴露的金属表面上形成保护性自对准缓冲层。 可以将第二反应物与保护性自对准缓冲层接触以在保护性自对准缓冲层上直接形成自对准电介质盖层。