公开(公告)号：US06983388B2

公开(公告)日：2006-01-03

申请号：US09865847

申请日：2001-05-25

申请人： Stefanos Kaxiras ,  Philip W. Diodato ,  Hubert Rae McLellan, Jr. ,  Girija Narlikar

发明人： Stefanos Kaxiras ,  Philip W. Diodato ,  Hubert Rae McLellan, Jr. ,  Girija Narlikar

IPC分类号： G06F1/32

CPC分类号： G11C5/143 ,  G11C11/417

摘要： A method and apparatus are disclosed for reducing leakage power in a cache memory. A cache decay technique is employed for both data and instruction caches that removes power from cache lines that have not been accessed for a predefined time interval, referred to as the decay interval. The cache-line granularity of the present invention permits a significant reduction in leakage power while at the same time preserving much of the performance of the cache. The decay interval is maintained using a timer that is reset each time the corresponding cache line is accessed. The decay interval may be fixed or variable. Once the decay interval timer exceeds a specified decay interval, power to the cache line is removed. Once power to the cache line is removed, the contents of the data and tag fields are allowed to decay and the valid bit associated with the cache line is reset. When a cache line is later accessed after being powered down by the present invention, a cache miss is incurred while the cache line is again powered up and the data is obtained from the next level of the memory hierarchy.

摘要翻译： 公开了一种用于减少高速缓冲存储器中的泄漏功率的方法和装置。 缓存衰减技术被用于数据和指令高速缓存，这些高速缓存从预定义的时间间隔（称为衰减间隔）中去除未被访问的高速缓存行的功率。 本发明的高速缓存线粒度允许显着降低泄漏功率，同时保持高速缓存的大部分性能。 使用每次访问相应的高速缓存行时重置的定时器来维持衰减间隔。 衰减间隔可以是固定的或可变的。 一旦衰减间隔定时器超过指定的衰减间隔，就删除高速缓存行的电源。 一旦去除了高速缓存线的电源，就允许数据和标签字段的内容衰减，并且与高速缓存行相关联的有效位被重置。 当通过本发明关闭高速缓存行之后，高速缓存未命中，同时高速缓存行再次通电并且从存储器层级的下一级获得数据。

公开(公告)号：US06559499B1

公开(公告)日：2003-05-06

申请号：US09477310

申请日：2000-01-04

申请人： Glenn B Alers ,  Philip W Diodato ,  Ruichen Liu

发明人： Glenn B Alers ,  Philip W Diodato ,  Ruichen Liu

IPC分类号： H01L27108

CPC分类号： H01L28/60 ,  H01L21/31116 ,  H01L21/3185 ,  H01L27/10814 ,  H01L27/10894

摘要： A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer. The metal for the top plate of the capacitor is then deposited over the interconnect layer. The top plate of the capacitor extends into the trench. The metal layer and barrier layer are then patterned to form the top plate of the capacitor.

摘要翻译： 公开了一种在半导体器件的互连层中制造沟槽电容器的工艺。 在该过程中，在互连层中形成至少一个互连，然后将其互相平坦化。 为了形成沟槽电容器，在互连的电介质材料中形成沟槽。 沟槽的底部与底层中的金属触点连通。 在互连层上形成阻挡层材料，并进行各向异性蚀刻，将阻挡层留在沟槽的侧壁上。 然后通过在互连层上沉积金属层形成电容器的下板。 然后对金属层进行各向异性蚀刻，去除互连层表面上的金属，并沿着沟槽周边离开金属。 然后将电容器介电层沉积在互连层上并随后被图案化。 另一层屏障材料沉积在互连层上。 然后将电容器的顶板的金属沉积在互连层上。 电容器的顶板延伸到沟槽中。 然后将金属层和阻挡层图案化以形成电容器的顶板。

公开(公告)号：US06272039B1

公开(公告)日：2001-08-07

申请号：US09498543

申请日：2000-02-04

申请人： James T. Clemens ,  Philip W. Diodato ,  Yiu-Huen Wong

发明人： James T. Clemens ,  Philip W. Diodato ,  Yiu-Huen Wong

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： An apparatus and method for constructing a temperature insensitive memory cell. This temperature insensitive memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. The temperature insensitive memory cell apparatus includes at least one transistor having a current leakage, and at least one capacitor electrically connected to the transistor. The capacitor acts as a load element for the memory cell. The capacitor has a temperature dependent capacitor leakage that tracks the current leakage of transistor as said at least one transistor as the transistor varies with temperature.

摘要翻译： 一种用于构建温度不敏感的存储单元的装置和方法。 如果使用特定的电容器和晶体管配置，该温度不敏感的存储器单元作为静态随机存取存储器（SRAM）单元工作。 温度不敏感的存储单元装置包括至少一个具有电流泄漏的晶体管，以及电连接到该晶体管的至少一个电容器。 电容器用作存储单元的负载元件。 电容器具有依赖于温度的电容器泄漏，其随着晶体管随着温度变化而跟踪晶体管的电流泄漏作为所述至少一个晶体管。

公开(公告)号：US5519350A

公开(公告)日：1996-05-21

申请号：US497350

申请日：1995-06-30

申请人： Philip W. Diodato ,  Harry T. Weston

发明人： Philip W. Diodato ,  Harry T. Weston

IPC分类号： H03K19/173 ,  G06F1/10 ,  H03K5/15 ,  H03K19/0175 ,  H03K19/018 ,  H04L25/02 ,  H03M1/04 ,  H01L25/00

CPC分类号： H04L25/0272 ,  H03K5/15046

摘要： In an electronic system such as an integrated circuit having a number of destination loads such as logic gates, signal is distributed along typically a zero'th level (e.g., polysilicon) electrical transmission line from an input terminal to the destination loads. The characteristics of the signal arriving at the destination loads are improved by (1) inserting an added electrical transmission line, and (2) connecting various nodes of the added electrical transmission line through auxiliary active devices, such as inverters, to various nodes on the zero'th level electrical transmission line. In one attractive arrangement, each of the auxiliary active devices has an electrical-current-drive capability that increases monotonically with the number of nodes intervening between it and the input terminal of the added electrical transmission line.

摘要翻译： 在具有诸如逻辑门等目的地负载的集成电路的电子系统中，信号通常沿着从输入端到目的地负载的第零级（例如多晶硅）电传输线分布。 通过（1）插入添加的电力传输线来改善到达目的地负载的信号的特性，以及（2）通过诸如逆变器的辅助有源设备将添加的电力传输线路的各个节点连接到 零级电力传输线。 在一个有吸引力的布置中，每个辅助有源器件具有电流驱动能力，该电流驱动能力随着其与所添加的电力传输线的输入端之间插入的节点的数量单调增加。

公开(公告)号：US06794694B2

公开(公告)日：2004-09-21

申请号：US09742314

申请日：2000-12-21

申请人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

发明人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  H01L21/76838 ,  H01L23/5223 ,  H01L27/10894 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

摘要翻译： 集成电路包括其上形成有半导体器件的半导体衬底及其上，位于衬底上的第一布线层，位于第一布线层上的第二布线层和电容器。 电容器具有延伸穿过第二布线层和至少部分第一布线层的金属基电荷存储电极。 布线层具有嵌入其中的互连线。

公开(公告)号：US6038163A

公开(公告)日：2000-03-14

申请号：US189131

申请日：1998-11-09

申请人： James T. Clemens ,  Philip W. Diodato ,  Yiu-Huen Wong

发明人： James T. Clemens ,  Philip W. Diodato ,  Yiu-Huen Wong

IPC分类号： H01L27/11 ,  G11C11/412 ,  G11C11/413 ,  H01L21/8244 ,  G11C11/00

CPC分类号： G11C11/412

摘要： An apparatus and method for constructing a capacitor loaded memory cell. This capacitor loaded memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. Normally, capacitors are not an obvious choice as a load device for a memory cell because the intrinsic nature of capacitors is one that blocks the flow of direct current, the invention takes into account the secondary effects such as leakage of a particular dielectric used in the construction of the capacitor to modify the current blocking nature of the capacitor.

摘要翻译： 一种用于构造电容器存储单元的装置和方法。 如果使用特定的电容器和晶体管配置，该电容器加载的存储单元作为静态随机存取存储器（SRAM）单元工作。 通常，电容器作为存储器单元的负载装置不是明显的选择，因为电容器的固有特性是阻止直流电流的本征特性，本发明考虑到二次效应，例如在 电容器的构造来修改电容器的电流阻塞性质。

公开(公告)号：US5063578A

公开(公告)日：1991-11-05

申请号：US586659

申请日：1990-09-24

申请人： Philip W. Diodato

发明人： Philip W. Diodato

IPC分类号： H03K5/00

CPC分类号： H03K5/00006

摘要： A digital logic circuit (100) is provided for multiplying, such as doubling, the frequency of an input clock pulse sequence of period T. The circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements (12, 13 in A1, A2, A3, . . . and B1, B2, B3, . . . ). Further, the n'th one of set of clocked latches (14, 15, 16 in A2, A4, A6, . . . ) derives its input from the 2n'th one of the delay elements in the first chain, where n is a running integer index (n=1,2,3, . . . ). The circuit (100) also includes a set of two-input logic gates (11), one of whose inputs (IN) is the output (OU) of a separate one of the logic elements (12, 13) in the second chain and the other of whose inputs is an output (MO) of a separate one of the latches (14, 15, 16). Each of the outputs of these logic gates (11) is fed to a multiple input output logic gate (25) whose output has a desired double-frequency feature (edges at T/4) relative to the frequency of the clocked pulse sequence (CLK).