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1.发明授权Apparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI bus 失效允许CPU数据总线或存储器数据总线或存储器数据总线访问PCI总线的装置
公开(公告)号：US5732226A
公开(公告)日：1998-03-24
申请号：US629011
申请日：1996-04-08
CPC分类号： G06F13/1605 , Y02B60/1228
摘要： A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.
摘要翻译： 链路系统控制器被插入在PCI总线与个人计算机系统的数据总线和存储器数据总线之间，以正常允许将写入信息从PCI总线传送到存储器数据总线上的DRAM存储器。 每当要求将数据传送到CPU数据总线时，CPU总线接口控制器要求从DRAM控制器释放系统。 只要DRAM控制器不将数据写入DRAM数据总线，DRAM控制器就可以向CPU总线接口授予许可或释放控制权。 当该释放被实现时，防止将写入数据传送到存储器数据总线，并且能够将数据传送到CPU数据总线。 这防止了CPU数据总线和存储器数据总线上的设备的同时切换，以减少噪声的产生; 使得IC系统设备的操作不受损害。
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公开(公告)号：US5737545A
公开(公告)日：1998-04-07
申请号：US651698
申请日：1996-05-21
IPC分类号： G06F13/362 , H01J13/00
CPC分类号： G06F13/362
摘要： A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.
摘要翻译： 一种方法和系统被设计为通过总线主控或者也包括PCI总线的系统中的直接存储器访问设备来保证ISA总线的可用性。 这通过将PCI总线上的锁定通过桥接器件到PCI配置空间寄存器的配置读取来实现。 锁定建立后，防止其他PCI设备锁定PCI总线上的任何其他资源。 PCI配置空间存在于ISA驻留设备可以生成访问的存储器或I / O范围之外。 因此，每当ISA驻留设备生成其访问时，它都是已知不处于锁定状态的设备。 因此，总线交易能够在ISA驻留设备预期的期限内完成。
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