公开(公告)号：US5732226A

公开(公告)日：1998-03-24

申请号：US629011

申请日：1996-04-08

申请人： Philip Wszolek ,  Rodney James Pesavento ,  Brian Neil Fall ,  James Crawford Steele

发明人： Philip Wszolek ,  Rodney James Pesavento ,  Brian Neil Fall ,  James Crawford Steele

IPC分类号： G06F13/16 ,  G06F13/36

CPC分类号： G06F13/1605 ,  Y02B60/1228

摘要： A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.

摘要翻译： 链路系统控制器被插入在PCI总线与个人计算机系统的数据总线和存储器数据总线之间，以正常允许将写入信息从PCI总线传送到存储器数据总线上的DRAM存储器。 每当要求将数据传送到CPU数据总线时，CPU总线接口控制器要求从DRAM控制器释放系统。 只要DRAM控制器不将数据写入DRAM数据总线，DRAM控制器就可以向CPU总线接口授予许可或释放控制权。 当该释放被实现时，防止将写入数据传送到存储器数据总线，并且能够将数据传送到CPU数据总线。 这防止了CPU数据总线和存储器数据总线上的设备的同时切换，以减少噪声的产生; 使得IC系统设备的操作不受损害。