公开(公告)号：US06782466B1

公开(公告)日：2004-08-24

申请号：US09449273

申请日：1999-11-24

申请人： James Crawford Steele ,  Desi Rhoden ,  George Crouse

发明人： James Crawford Steele ,  Desi Rhoden ,  George Crouse

IPC分类号： G06F1200

CPC分类号： G06F12/0215

摘要： A memory access approach optimizes memory address mapping for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is directed to a process of accessing data in a plurality of addressable banks of memory cells. The process involves accessing the memory cells by addressing arrays in the banks via column and row bits, and directing the address and control signals so that the addressable column address and row address bits are selected with a lower order group of the address bits directed to select the column address bits, and the next highest group of the address bits directed to select bank address bits. The next highest group of the address bits are directed to select the row address bits.

摘要翻译： 存储器访问方法优化存储器地址映射以访问虚拟存储器布置中的数据，其中多组数据立即打开。 一个具体实现涉及访问存储器单元的多个可寻址组中的数据的过程。 该过程涉及通过列和行位对存储体中的数组进行寻址来存取存储器单元，并且引导地址和控制信号，使得可寻址的列地址和行地址位被选择为指向要选择的地址位的低阶组 列地址位，以及指向选择存储区地址位的地址位的下一个最高组。 下一个最高的地址位组用于选择行地址位。

公开(公告)号：US5732226A

公开(公告)日：1998-03-24

申请号：US629011

申请日：1996-04-08

申请人： Philip Wszolek ,  Rodney James Pesavento ,  Brian Neil Fall ,  James Crawford Steele

发明人： Philip Wszolek ,  Rodney James Pesavento ,  Brian Neil Fall ,  James Crawford Steele

IPC分类号： G06F13/16 ,  G06F13/36

CPC分类号： G06F13/1605 ,  Y02B60/1228

摘要： A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.

摘要翻译： 链路系统控制器被插入在PCI总线与个人计算机系统的数据总线和存储器数据总线之间，以正常允许将写入信息从PCI总线传送到存储器数据总线上的DRAM存储器。 每当要求将数据传送到CPU数据总线时，CPU总线接口控制器要求从DRAM控制器释放系统。 只要DRAM控制器不将数据写入DRAM数据总线，DRAM控制器就可以向CPU总线接口授予许可或释放控制权。 当该释放被实现时，防止将写入数据传送到存储器数据总线，并且能够将数据传送到CPU数据总线。 这防止了CPU数据总线和存储器数据总线上的设备的同时切换，以减少噪声的产生; 使得IC系统设备的操作不受损害。