公开(公告)号：US5629230A

公开(公告)日：1997-05-13

申请号：US509782

申请日：1995-08-01

申请人： Pierre C. Fazan ,  Nanseng Jeng ,  David L. Dickerson

发明人： Pierre C. Fazan ,  Nanseng Jeng ,  David L. Dickerson

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： A semiconductor processing method of forming a field oxide region on a semiconductor substrate includes, a) providing a patterned first masking layer over a desired active area region of a semiconductor substrate, the first masking layer having at least one side edge; b) providing a silicon sidewall spacer over the side edge of the patterned first masking layer, the silicon sidewall spacer having a laterally outward projecting foot portion; c) oxidizing the substrate and the silicon sidewall spacer to form a field oxide region on the substrate; d) stripping the first masking layer from the substrate; and e) providing a gate oxide layer over the substrate. The invention enables taking advantage of process techniques which minimize the size of field oxide bird's beaks without sacrificing upper field oxide topography.

摘要翻译： 在半导体衬底上形成场氧化物区域的半导体处理方法包括：a）在半导体衬底的期望的有源区域上提供图案化的第一掩模层，所述第一掩模层具有至少一个侧边; b）在图案化的第一掩蔽层的侧边缘上提供硅侧壁间隔物，硅侧壁间隔件具有横向向外突出的脚部; c）氧化所述衬底和所述硅侧壁间隔物以在所述衬底上形成场氧化物区域; d）从衬底剥离第一掩蔽层; 以及e）在所述衬底上提供栅氧化层。 本发明能够利用在不牺牲上部场氧化物形貌的情况下使场氧化物鸟的喙的尺寸最小化的工艺技术。

公开(公告)号：US5933754A

公开(公告)日：1999-08-03

申请号：US874642

申请日：1997-06-13

申请人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

发明人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/14 ,  H01L23/522 ,  H01L21/308

CPC分类号： H01L21/76843 ,  H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002

摘要： A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer of conductive material atop the wafer and to within the facet etched contact opening to fill the contact opening; and h) etching the conductive material and first material layer inwardly to at least the angled sidewalls' inner base to define an electrically conductive contact plug which electrically connects with the substrate.

摘要翻译： 相对于晶片形成导电接触插塞的半导体处理方法包括：a）提供要进行电连接的基板; b）在基板顶部沉积一层第一材料至所选择的厚度; c）图案掩蔽第一材料层以形成所需的接触开口; d）蚀刻通过第一材料层以形成通过其与基板电连接的接触开口，接触开口具有最外区域; e）在蚀刻之后形成接触开口，从第一材料层去除掩模; f）在从第一材料层去除掩模之后，相对于接触开口小面溅射蚀刻到第一材料层中以提供向外成角度的侧壁，这有效地加宽了接触开口最外区域，向外成角度的侧壁具有内部基部， 与原来的接触开口; g）在晶片顶部和面蚀刻的接触开口内沉积导电材料层以填充接触开口; 以及h）将所述导电材料和所述第一材料层向内蚀刻到至少所述成角度的侧壁的内部基底，以限定与所述基底电连接的导电接触插塞。

公开(公告)号：US06835634B1

公开(公告)日：2004-12-28

申请号：US09037945

申请日：1998-03-10

申请人： Pierre C. Fazan ,  Viju K. Mathews ,  Nanseng Jeng

发明人： Pierre C. Fazan ,  Viju K. Mathews ,  Nanseng Jeng

IPC分类号： H01L21762

CPC分类号： H01L21/76202

摘要： A field isolation process performed on a silicon wafer is carried out by high pressure oxidation. Using oxygen rather than water vapor as the oxidant substantially eliminates nitride inclusions via the Kooi effect. Preferred high pressure field oxidation processes simplify all CMOS flows by eliminating the need for sacrificial oxide growth and removal steps.

摘要翻译： 通过高压氧化进行在硅晶片上进行的场隔离处理。 使用氧气而不是水蒸气作为氧化剂，基本上消除了通过Kooi效应的氮化物夹杂物。 优选的高压场氧化工艺通过消除对牺牲氧化物生长和去除步骤的需要来简化所有CMOS流程。

公开(公告)号：US5726092A

公开(公告)日：1998-03-10

申请号：US855764

申请日：1997-05-23

申请人： Viju Mathews ,  Pierre C. Fazan ,  Nanseng Jeng

发明人： Viju Mathews ,  Pierre C. Fazan ,  Nanseng Jeng

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： A semiconductor processing method of forming a pair of adjacent field oxide regions includes, i) providing a sacrificial pad oxide layer to a thickness of from 20 Angstroms to 100 Angstroms; ii) providing a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region, the layer having a thickness of from 500 Angstroms to 3000 Angstroms and comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; iii) oxidizing portions of the substrate unmasked by the masking layer in an O.sub.2 ambient at a pressure of at least 15 atmospheres to form at least one pair of adjacent field oxide regions, the ambient being substantially void of H.sub.2 O during the oxidizing, the formed field oxide regions having a location of maximum thickness of from 1500 Angstroms to 3000 Angstroms; iv) stripping the masking layer from the substrate; v) providing a gate oxide layer over the active area between the pair of field oxide regions; and vi) etching portions of the field oxide regions prior to providing the gate oxide, such etching resulting in removal of a total of from 250 to 1000 Angstroms of oxide from the field oxide regions prior to provision of the gate oxide, such etching resulting in a maximum width of the respective field oxide regions of from 0.20 to 0.40 micron and a minimum pitch of the adjacent pair of field oxide regions of from 0.5 to 0.7 micron.

摘要翻译： 形成一对相邻场氧化物区域的半导体处理方法包括：i）提供厚度为20埃至100埃的牺牲衬垫氧化物层; ii）在所述牺牲衬垫氧化物层上方并且在期望的有源区域区域上提供具有500埃至3000埃厚度的图案化掩模层，并且包括一对相邻的掩模块，其具有0.5微米到 0.7微米; iii）在至少15个大气压的压力下，氧气环境中被掩蔽层未掩蔽的衬底氧化部分以形成至少一对相邻的场氧化物区域，在氧化过程中环境基本上不含H 2 O. 具有最大厚度为1500埃至3000埃的位置的氧化物区域; iv）从衬底剥离掩模层; v）在一对场氧化物区域之间的有源区域上提供栅极氧化层; 以及vi）在提供栅极氧化物之前蚀刻场氧化物区域的部分，这样的蚀刻导致在提供栅极氧化物之前从场氧化物区域中去除总共250至1000埃的氧化物，这样的蚀刻导致 相应的场氧化物区域的最大宽度为0.20至0.40微米，相邻的一对场氧化物区域的最小间距为0.5至0.7微米。

公开(公告)号：US06611038B2

公开(公告)日：2003-08-26

申请号：US10029500

申请日：2001-12-19

申请人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

发明人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan

IPC分类号： H01L2176

CPC分类号： H01L21/76202

摘要： A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.

公开(公告)号：US5940692A

公开(公告)日：1999-08-17

申请号：US780235

申请日：1997-01-08

申请人： Nanseng Jeng ,  Viju K. Mathews ,  Pierre C. Fazan

发明人： Nanseng Jeng ,  Viju K. Mathews ,  Pierre C. Fazan

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/84

CPC分类号： H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

摘要： A method of reducing diffusion of impurity dopants within a semiconductive material beneath a field effect transistor gate in a process of forming a field effect transistor includes, a) providing a bulk monocrystalline silicon substrate; b) providing a gate oxide layer over the silicon substrate; c) providing a patterned gate over the gate oxide layer, the gate having sidewalls; d) providing a pair of diffusion regions within the silicon substrate adjacent the gate sidewalls; and e) subjecting the wafer to an oxidizing atmosphere at a pressure of from about 5 atmospheres to about 30 atmospheres and at a temperature of from about 650.degree. C. to about 750.degree. C. for a period of time from about 5 minutes to about 30 minutes effective, i) to oxidize the gate sidewalls, ii) to oxidize the semiconductive material substrate adjacent the gate sidewalls, and iii) to thicken the gate oxide layer adjacent the gate sidewalls.

摘要翻译： 在形成场效应晶体管的过程中，减小场效应晶体管栅极下方的半导体材料内的杂质掺杂剂的扩散的方法包括：a）提供大块单晶硅衬底; b）在硅衬底上提供栅氧化层; c）在所述栅极氧化物层上提供图案化栅极，所述栅极具有侧壁; d）在邻近栅极侧壁的硅衬底内提供一对扩散区; 和e）使晶片在约5个大气压至约30个大气压和约650℃至约750℃的温度下经受氧化气氛约5分钟至约5分钟 30分钟有效，i）氧化栅极侧壁，ii）氧化与栅极侧壁相邻的半导体材料基板，以及iii）增加邻近栅极侧壁的栅极氧化物层。

公开(公告)号：US5891788A

公开(公告)日：1999-04-06

申请号：US747797

申请日：1996-11-14

申请人： Pierre C. Fazan ,  Viju K. Mathews ,  Nanseng Jeng

发明人： Pierre C. Fazan ,  Viju K. Mathews ,  Nanseng Jeng

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202

摘要： A technique for producing an isolation structure in a semiconductor substrate wherein lateral encroachment, i.e., bird's beak formation, under a masking stack is limited. The disclosed embodiment comprises growing a layer of pad oxide on a silicon substrate and then depositing a layer of silicon nitride on the layer of pad oxide. The nitride is then patterned and etched to define a masking stack and a region of the substrate wherein the isolation structure is to be formed. The pad oxide is then removed from the region and is also partially removed under the nitride stack, thus forming a cavity. A re-ox oxide layer is then grown over the substrate, followed by the growth of a spacer layer. The spacer layer is comprised of either polysilicon or silicon nitride. Subsequently, the isolation structure is grown using high pressure oxidation techniques, which results in the oxidation structure growing sufficiently fast that the spacer layer in the cavity is not oxidized. Lateral encroachment is thus reduced and punchthrough of the bird's beak region is prevented.

摘要翻译： 用于在半导体衬底中制造隔离结构的技术，其中在遮蔽叠层下面的侧向侵入，即鸟的喙形成被限制。 所公开的实施例包括在硅衬底上生长衬垫氧化物层，然后在衬垫氧化物层上沉积氮化硅层。 然后对氮化物进行构图和蚀刻以限定掩模叠层和衬底的区域，其中将形成隔离结构。 然后从该区域移除焊盘氧化物，并且在氮化物堆叠下也部分去除焊盘氧化物，从而形成空腔。 然后将氧化物氧化物层生长在衬底上，随后生长间隔层。 间隔层由多晶硅或氮化硅组成。 随后，使用高压氧化技术生长隔离结构，这导致氧化结构生长足够快，使空腔中的间隔层不被氧化。 因此，横向侵占减少，鸟喙区的穿透被阻止。

公开(公告)号：US5837378A

公开(公告)日：1998-11-17

申请号：US527026

申请日：1995-09-12

申请人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan ,  Thomas A. Figura

发明人： Viju K. Mathews ,  Nanseng Jeng ,  Pierre C. Fazan ,  Thomas A. Figura

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202

摘要： A process for reducing stress during processing of semiconductor wafers comprising the steps of depositing a masking stack on a top and a bottom surface of the wafer and then removing at least a portion of the masking stack on the bottom surface prior to forming isolation regions on the top surface of the semiconductor wafer. In one embodiment, silicon nitride is formed on the top and the bottom surface of a silicon wafer. The silicon nitride is then patterned and etched on the top surface of the wafer to expose regions of the underlying silicon for field oxide formation. Prior to the field oxidation formation on the top side of the wafer, the silicon nitride layer on the bottom side of the wafer is removed so that a layer of silicon dioxide is formed on the bottom surface of the wafer during field oxidation formation. The layer of silicon dioxide on the bottom surface of the wafer reduces the stress in the regions of the silicon wafer adjacent the top surface of the wafer and thereby reduces the formation of stress induced defects in this region of the silicon wafer. The layer of silicon dioxide on the bottom surface of the wafer can then be removed.

摘要翻译： 一种用于在半导体晶片的加工期间减小应力的方法，包括以下步骤：在晶片的顶部和底部表面上沉积掩模叠层，然后在形成隔离区域之前去除底表面上的掩模叠层的至少一部分 半导体晶片的顶表面。 在一个实施例中，在硅晶片的顶表面和底表面上形成氮化硅。 然后将氮化硅图案化并蚀刻在晶片的顶表面上以暴露下面的硅的区域用于场氧化物形成。 在晶片顶部的场氧化形成之前，去除晶片底侧的氮化硅层，使得在场氧化形成期间在晶片的底表面上形成一层二氧化硅。 在晶片的底表面上的二氧化硅层减小了与晶片顶表面相邻的硅晶片的区域中的应力，从而减小了硅晶片的该区域中应力引起的缺陷的形成。 然后可以去除晶片底表面上的二氧化硅层。

公开(公告)号：US5674776A

公开(公告)日：1997-10-07

申请号：US544785

申请日：1995-10-18

申请人： Viju Mathews ,  Pierre C. Fazan ,  Nanseng Jeng

发明人： Viju Mathews ,  Pierre C. Fazan ,  Nanseng Jeng

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76202 ,  Y10S438/911 ,  Y10S438/981

摘要： A semiconductor processing method of forming a pair of adjacent field oxide regions includes, i) providing a sacrificial pad oxide layer to a thickness of from 20 Angstroms to 100 Angstroms; ii) providing a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region, the layer having a thickness of from 500 Angstroms to 3000 Angstroms and comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; iii) oxidizing portions of the substrate unmasked by the masking layer in an H.sub.2 O steam ambient at a pressure of from about 0.5 atmosphere to about 2 atmospheres and at a temperature of from about 900.degree. C. to about 1200.degree. C. to form at least one pair of adjacent field oxide regions, the formed field oxide regions having a location of maximum thickness of from 1500 Angstroms to 3000 Angstroms; iv) stripping the masking layer from the substrate; v) providing a gate oxide layer over the active area between the pair of field oxide regions; and vi) etching portions of the field oxide regions prior to providing the gate oxide, such etching resulting in removal of a total of from 250 to 1000 Angstroms of oxide from the field oxide regions prior to provision of the gate oxide, such etching resulting in a maximum width of the respective field oxide regions of from 0.20 to 0.40 micron and a minimum pitch of the adjacent pair of field oxide regions of from 0.5 to 0.7 micron.

摘要翻译： 形成一对相邻场氧化物区域的半导体处理方法包括：i）提供厚度为20埃至100埃的牺牲衬垫氧化物层; ii）在所述牺牲衬垫氧化物层上方并且在期望的有源区域区域上提供具有500埃至3000埃厚度的图案化掩模层，并且包括一对相邻的掩模块，其具有0.5微米到 0.7微米; iii）在约0.5大气压至约2个大气压和约900℃至约1200℃的温度下，在H 2 O蒸气环境中，通过掩蔽层未掩蔽的衬底的氧化部分至少形成 一对相邻的场氧化物区域，所形成的场氧化物区域具有最大厚度为1500埃至3000埃的位置; iv）从衬底剥离掩模层; v）在一对场氧化物区域之间的有源区域上提供栅极氧化层; 以及vi）在提供栅极氧化物之前蚀刻场氧化物区域的部分，这样的蚀刻导致在提供栅极氧化物之前从场氧化物区域中去除总共250至1000埃的氧化物，这样的蚀刻导致 相应的场氧化物区域的最大宽度为0.20至0.40微米，相邻的一对场氧化物区域的最小间距为0.5至0.7微米。

公开(公告)号：US5637514A

公开(公告)日：1997-06-10

申请号：US544599

申请日：1995-10-18

申请人： Nanseng Jeng ,  Viju K. Mathews ,  Pierre C. Fazan

发明人： Nanseng Jeng ,  Viju K. Mathews ,  Pierre C. Fazan

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8232 ,  H01L21/84

CPC分类号： H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

摘要： A method of reducing diffusion of impurity dopants within a semiconductive material beneath a field effect transistor gate in a process of forming a field effect transistor includes, a) providing a bulk monocrystalline silicon substrate; b) providing a gate oxide layer over the silicon substrate; c) providing a patterned gate over the gate oxide layer, the gate having sidewalls; d) providing a pair of diffusion regions within the silicon substrate adjacent the gate sidewalls; and e) subjecting the wafer to an oxidizing atmosphere at a pressure of from about 5 atmospheres to about 30 atmospheres and at a temperature of from about 650.degree. C. to about 750.degree. C. for a period of time from about 5 minutes to about 30 minutes effective, i) to oxidize the gate sidewalls, ii) to oxidize the semiconductive material substrate adjacent the gate sidewalls, and iii) to thicken the gate oxide layer adjacent the gate sidewalls.

摘要翻译： 在形成场效应晶体管的过程中，减小场效应晶体管栅极下方的半导体材料内的杂质掺杂剂的扩散的方法包括：a）提供大块单晶硅衬底; b）在硅衬底上提供栅氧化层; c）在所述栅极氧化物层上提供图案化栅极，所述栅极具有侧壁; d）在邻近栅极侧壁的硅衬底内提供一对扩散区; 和e）使晶片在约5个大气压至约30个大气压和约650℃至约750℃的温度下经受氧化气氛约5分钟至约5分钟 30分钟有效，i）氧化栅极侧壁，ii）氧化与栅极侧壁相邻的半导体材料基板，以及iii）增加邻近栅极侧壁的栅极氧化物层。