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    Apparatus for generating and checking the error correction codes of messages in a message switching system
    1.
    发明授权
    Apparatus for generating and checking the error correction codes of messages in a message switching system 失效
    用于在消息交换系统中生成和检查消息的纠错码的装置

    公开(公告)号：US5467359A

    公开(公告)日：1995-11-14

    申请号：US24061

    申请日：1993-03-01

    申请人： Pierre J. Huon ,  Philippe Jachimcsyk ,  Gerard Barucchi ,  Jean Calvignac ,  Fabrice Verplanken

    发明人： Pierre J. Huon ,  Philippe Jachimcsyk ,  Gerard Barucchi ,  Jean Calvignac ,  Fabrice Verplanken

    IPC分类号： G06F11/10 ,  G06F13/00 ,  H03M13/00 ,  H04L1/00

    CPC分类号： H04L1/0057 ,  H04L1/0041 ,  H04L2001/0094

    摘要： An error correction apparatus includes an error control circuit which computes for each burst of a message (for a destination unit) an error correction code as a function of an initial error correction code at the first burst of the message or of the error correction code of the previous burst and of the data bytes of the burst. The burst error correction code is sent on a medium which is separate from the data transport medium as a companion of the burst. Also, the error control circuit receives the burst error correction code from an origin unit and generates the burst error correction code to be compared with the received burst error correction code. If a mismatch is detected, the burst found in error is flagged.

    摘要翻译： 纠错装置包括：错误控制电路，用于根据消息的第一个突发或者纠错码的初始纠错码，对消息的每个突发（对于目的地单元）计算纠错码，作为初始纠错码的函数 先前的突发和突发的数据字节。 突发纠错码在与数据传输介质分离的介质上发送，作为突发的伴侣。 此外，误差控制电路从原点单元接收脉冲串纠错码，并产生与接收脉冲串纠错码进行比较的脉冲串纠错码。 如果检测到不匹配，则会发现错误中发现的突发状况。

    Switching system for simultaneously transferring data between data processing units
    2.
    发明授权
    Switching system for simultaneously transferring data between data processing units 失效
    用于在数据处理单元之间同时传输数据的切换系统

    公开(公告)号：US5392401A

    公开(公告)日：1995-02-21

    申请号：US5425

    申请日：1993-01-21

    申请人： Gerard Barucchi ,  Jean Calvignac ,  Daniel Orsatti ,  Andre Tracol

    发明人： Gerard Barucchi ,  Jean Calvignac ,  Daniel Orsatti ,  Andre Tracol

    IPC分类号： G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F13/00 ,  G06F13/14

    CPC分类号： G06F15/17375

    摘要： The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

    摘要翻译： 该系统在包括从N个数据处理单元（8）中选择的原始单元和目标单元的单元对之间执行数据分组的优化数量的同时传送。 每个数据处理单元包括一组出站队列，其中一个出站队列与其可以发送数据分组的数据处理单元中的每一个相关联，用于存储要由数据处理单元发送到数据处理单元的数据分组 有一个出站队列。 响应于在先前的突发期间由调度器4产生的控制信号，在数据交换机6的时间突发Ti + 1的控制下，在由线路16-1至16-N上的单元发送到数据交换的切换控制信号的情况下， 时间Ti 调度器运行选择算法，其给出每个单位在给定时间段内作为原始单位的相等概率。

    Synchronization circuit for a synchronous switching system
    3.
    发明授权
    Synchronization circuit for a synchronous switching system 失效
    用于同步切换系统的同步电路（SYNCHRONISATION CIRCUIT FOR SYNCCHRONOUS SWITCHING SYSTEM）

    公开(公告)号：US5134636A

    公开(公告)日：1992-07-28

    申请号：US657906

    申请日：1991-02-20

    申请人： Gerard Barucchi ,  Jean Calvignac ,  Jose Galcera ,  Gilles Toubol ,  Andre Tracol ,  Daniel Orsatti

    发明人： Gerard Barucchi ,  Jean Calvignac ,  Jose Galcera ,  Gilles Toubol ,  Andre Tracol ,  Daniel Orsatti

    IPC分类号： G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

    CPC分类号： H04J3/0629

    摘要： The synchronization circuit resynchronizes the data bits received from remote devices on line or link (20-1) with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in an n-bit cyclic buffer (114-1) with the received bit clock CS. The arranged bits are sequentially picked at the opposite buffer position with the central clock CO. The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

    Programmable multifield parser packet
    4.
    发明授权
    Programmable multifield parser packet 失效
    可编程多字段解析器包

    公开(公告)号：US08681819B2

    公开(公告)日：2014-03-25

    申请号：US13017963

    申请日：2011-01-31

    申请人： Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

    发明人： Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

    IPC分类号： G01R31/08 ,  H04J3/24

    CPC分类号： H04L69/22

    摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.

    摘要翻译： 一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小） 由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

    Systems and methods for multi-frame control blocks
    9.
    发明申请
    Systems and methods for multi-frame control blocks 有权

    公开(公告)号：US20060206684A1

    公开(公告)日：2006-09-14

    申请号：US11076218

    申请日：2005-03-09

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    IPC分类号： G06F12/00 ,  G06F9/34

    CPC分类号： H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

    摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.