Cyphering/decyphering performed by an integrated circuit
    1.
    发明授权
    Cyphering/decyphering performed by an integrated circuit 失效
    由集成电路执行的Cyphering / decyphering

    公开(公告)号:US07403620B2

    公开(公告)日:2008-07-22

    申请号:US10611254

    申请日:2003-07-01

    IPC分类号: H04L9/00

    摘要: A method of cyphering and/or decyphering, by an integrated circuit, of a digital input code by means of several keys, comprising: dividing the code into several data blocks of same dimensions; and applying to said blocks several turns of a cyphering or decyphering comprising submitting each block to at least one same non-linear transformation and of subsequently combining each block with a different key at each turn, the operands being masked, upon execution of the method, by at least one first random number having the size of the code and all the blocks of which have the same value by combining, by an XOR-type function, the input and output blocks of the non-linear transformation with said random number.

    摘要翻译: 一种通过集成电路对几个键进行数字输入代码的连接和/或解粘的方法,包括:将代码划分成相同尺寸的多个数据块; 以及向所述块应用多个匝数或次衰减,包括将每个块提交至少一个相同的非线性变换,并且随后在每一匝上将每个块与不同的密钥组合,所述操作数被屏蔽,在执行该方法时, 通过由XOR类型函数组合具有所述随机数的非线性变换的输入和输出块的具有代码大小和其所有块具有相同值的至少一个第一随机数。

    Processor for executing an AES-type algorithm
    2.
    发明授权
    Processor for executing an AES-type algorithm 有权
    用于执行AES类型算法的处理器

    公开(公告)号:US08102997B2

    公开(公告)日:2012-01-24

    申请号:US11547195

    申请日:2004-03-29

    IPC分类号: H04L9/28 H04K1/00

    摘要: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

    摘要翻译: 一种用于执行Rijndeal算法的处理器,该Rijndeal算法将多个加密回合应用于数据块阵列,以便获得相同大小的阵列,每轮涉及密钥块阵列和数据块替换表,其中所述处理器包括:第一 输入寄存器(102),其包含输入数据块列; 包含输出数据块列或中间块列的输出寄存器(111); 包含密钥块列或中间数据块的第二输入寄存器(101); 块替换元件(104)在第一寄存器中的选择(103)之后的时间接收数据一个块,并为每个块提供一列块; 向替代电路列块施加循环置换的元件(109); 以及将置换电路列块与第二寄存器的内容组合的异或组合元件(110),所述组合的结果被加载到输出寄存器中。

    Processor for Executing an Aes-Type Algorithm
    3.
    发明申请
    Processor for Executing an Aes-Type Algorithm 有权
    用于执行Aes类型算法的处理器

    公开(公告)号:US20080285745A1

    公开(公告)日:2008-11-20

    申请号:US11547195

    申请日:2004-03-29

    IPC分类号: H04L9/06

    摘要: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

    摘要翻译: 一种用于执行Rijndeal算法的处理器,该Rijndeal算法将多个加密回合应用于数据块阵列,以便获得相同大小的阵列,每轮涉及密钥块阵列和数据块替换表,其中所述处理器包括:第一 输入寄存器(102),其包含输入数据块列; 包含输出数据块列或中间块列的输出寄存器(111); 包含密钥块列或中间数据块的第二输入寄存器(101); 块替换元件(104)在第一寄存器中的选择(103)之后的时间接收数据一个块,并为每个块提供一列块; 向替代电路列块施加循环置换的元件(109); 以及将置换电路列块与第二寄存器的内容组合的异或组合元件(110),所述组合的结果被加载到输出寄存器中。

    Masking of binary words processed by an integrated circuit
    4.
    发明授权
    Masking of binary words processed by an integrated circuit 有权
    由集成电路处理的二进制字的掩码

    公开(公告)号:US08635460B2

    公开(公告)日:2014-01-21

    申请号:US11304236

    申请日:2005-12-14

    IPC分类号: G06F11/30 G06F12/14

    摘要: A method and a circuit for masking a digital word by application of a random bijection, including applying at least one first operation including selecting a non-disjoint subset of the word having its position and size depending on a first random quantity, and assigning to each bit of the subset, the state of the bit having a symmetrical position with respect to the middle of the subset, to obtain a masked digital quantity.

    摘要翻译: 一种用于通过应用随机双射屏蔽数字字的方法和电路,包括应用至少一个第一操作,包括根据第一随机数选择具有其位置和大小的字的非不相交子集,并分配给每个 该比特的状态相对于子集的中间具有对称位置,以获得掩蔽的数字量。

    Checking of the skew constancy of a bit flow
    5.
    发明授权
    Checking of the skew constancy of a bit flow 有权
    检查位流的偏斜常数

    公开(公告)号:US08554813B2

    公开(公告)日:2013-10-08

    申请号:US12852853

    申请日:2010-08-09

    IPC分类号: G06F7/58

    CPC分类号: G06F7/58 G06F7/588 H03K3/84

    摘要: A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element.

    摘要翻译: 一种用于检测源自起始位流的归一化的至少一个第一元素的第一输出位流的等能特性损失的方法和电路,包括分析归一化元件的流量。

    Protection of the execution of a program
    7.
    发明授权
    Protection of the execution of a program 有权
    保护程序的执行

    公开(公告)号:US07941639B2

    公开(公告)日:2011-05-10

    申请号:US11481432

    申请日:2006-07-05

    IPC分类号: G06F9/30

    摘要: A method for protecting the execution of a main program against possible traps, including, on occurrence of an instruction from the main program, starting a time counter of a given count according to next instructions of the main program, and executing, once the counter has reached its count, at least one instruction of a secondary program from which the result of the main program depends.

    摘要翻译: 一种用于保护主程序的执行免受可能的陷阱的方法,包括在发生来自主程序的指令时,根据主程序的下一个指令启动给定计数的时间计数器,一旦计数器具有 达到其计数,至少一个辅助程序的指令,主程序的结果从该程序所依赖。

    Checking of a bit flow
    8.
    发明授权
    Checking of a bit flow 有权
    检查位流

    公开(公告)号:US07734672B2

    公开(公告)日:2010-06-08

    申请号:US11166565

    申请日:2005-06-24

    IPC分类号: G06F1/02

    CPC分类号: H03K3/84

    摘要: A method and a circuit for detecting a possible loss of the equiprobable character of a first output bit flow originating from at least one first normalization element of an initial bit flow, consisting of submitting the initial flow to at least one second normalization element of a nature different from the first one, pairing, bit to bit, the flows originating from the two elements, and checking the equidistribution of the different state pairs.

    摘要翻译: 一种用于检测源自初始比特流的至少一个第一归一化元素的第一输出比特流的等能特性的可能损失的方法和电路,其包括将初始流提交给自然的至少一个第二归一化元素 与第一个不同,配对,比特,比特,来自两个元素的流,以及检查不同状态对的等分布。

    Masking of binary words processed by an integrated circuit
    9.
    发明申请
    Masking of binary words processed by an integrated circuit 有权
    由集成电路处理的二进制字的掩码

    公开(公告)号:US20060125664A1

    公开(公告)日:2006-06-15

    申请号:US11304236

    申请日:2005-12-14

    IPC分类号: H03M7/00

    摘要: A method and a circuit for masking a digital word by application of a random bijection, including applying at least one first operation including selecting a non-disjoint subset of the word having its position and size depending on a first random quantity, and assigning to each bit of the subset, the state of the bit having a symmetrical position with respect to the middle of the subset, to obtain a masked digital quantity.

    摘要翻译: 一种用于通过应用随机双射屏蔽数字字的方法和电路,包括应用至少一个第一操作,包括根据第一随机数选择具有其位置和大小的字的非不相交子集,并分配给每个 该比特的状态相对于子集的中间具有对称位置,以获得掩蔽的数字量。