摘要:
Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-integer value. The multiplier value is determined by extracting information from a first portion of a bitfield based on the scaled-integer value. The scale value is determined by extracting information from a second portion of the bitfield based on the scaled-integer value. The first and second portions of the bitfield are configurable to include signed integer values. The example method then performs an arithmetic operation based on the multiplier value and the scale value.
摘要:
Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from instruction memory during a runtime phase.
摘要:
Methods and apparatus for determining approximating polynomials using instruction-embedded coefficients are disclosed. In particular, the methods and apparatus use a plurality of coefficient values stored in a plurality of instructions. The coefficient values are associated with a runtime approximating polynomial of a K-th root family function. The coefficient values and the instructions stored in an instruction memory enable the processor system to determine a K-th root family function approximation value based on the runtime approximating polynomial.
摘要:
Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from instruction memory during a runtime phase.
摘要:
Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extracts a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent scaling value. The residuary subset bitfield value is part of a range of contiguous bits that is associated with upper and lower boundary bit-position values that are part of the compound exponent scaling value. The methods and apparatus determine the remainder value based on the residuary subset bitfield value.
摘要:
A method for performing shale gas operation is disclosed. The method may include drilling a first well, performing a fracturing operation in the well, recovering shale gas from the first well, supplying at least part of the shale gas recovered from the well to an electrical generator, generating electricity using the generator, and transferring the generated electricity to drilling equipment used to drill a second well.
摘要:
A method for performing shale gas operation is disclosed. The method may include drilling a first well, performing a fracturing operation in the well, recovering shale gas from the first well, supplying at least part of the shale gas recovered from the well to an electrical generator, generating electricity using the generator, and transferring the generated electricity to drilling equipment used to drill a second well.
摘要:
Methods and apparatus to provide rounding of a binary integer are described. In one embodiment, a value that indicates whether a divisor divides a binary integer is extracted from a product of the binary integer and a scaled approximate reciprocal of the divisor.
摘要:
An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate S1, where S1 is the sum of an integer k, the exponent of a floating point value A, and the exponent of a floating point value B. The exponent unit also includes a comparator to generate E1, where E1 is the greater of S1 and the exponent of a floating point value C. The apparatus also includes a partial multiplier, a shifter, and a second adder. The partial multiplier generates the partial products of the mantissas of A and B. The shifter aligns the partial products and the mantissa of C, based on E1. The second adder adds the aligned partial products and the mantissa of C. The apparatus is able to generate not only (A*B+C), but is enhanced to also be able to generate (2k*A*B+C) and the closest integer to (2k*A*B) in two's complement or floating point format.
摘要翻译:公开了一种用于执行增强的融合乘法运算的装置,方法和系统。 在一个实施例中,装置包括指数单元。 指数单元包括用于产生S 1的第一加法器,其中S 1是整数k,浮点值A的指数和浮点值B的指数之和。指数单元还包括比较器 产生E 1,其中E 1是S 1中的较大值和浮点值C的指数。该装置还包括部分乘法器,移位器和第二加法器。 部分乘法器产生A和B的尾数的部分乘积。移位器基于E 1对齐部分积和C的尾数。第二加法器将对齐的部分乘积和C的尾数相加。该装置能够 不仅产生(A * B + C),而且被增强以也能够生成(2≤K* A * B + C)和最接近的整数到(2 < / SUP> * A * B)二进制补码或浮点格式。
摘要:
Methods, apparatus, and articles of manufacture for determining quotient values are disclosed. An example method identifies a reciprocal value of a divisor value. A bias value is then identified and a biased quotient value is determined based on a dividend value, the reciprocal value, and at least a portion of the bias value. A quotient value is then determined based on the biased quotient value.