公开(公告)号：US08039367B2

公开(公告)日：2011-10-18

申请号：US12465636

申请日：2009-05-13

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L21/00 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L22/34 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction.

Abstract translation: 公开了划线结构。 划线结构包括具有管芯区域的半导体衬底，设置在管芯区域外部的管芯密封环区域，设置在管芯密封环区域外部的划线区域和形成在划线区域上的切割路径。 优选地，切割路径的中心线沿着第一方向偏离划线区域的中心线。

公开(公告)号：US20090001522A1

公开(公告)日：2009-01-01

申请号：US11771122

申请日：2007-06-29

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L29/02

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths.

Abstract translation: 描述了设置在管芯中并围绕管芯的集成电路区域的管芯密封环。 模具密封环具有至少两个不同的局部宽度。

公开(公告)号：US20080142997A1

公开(公告)日：2008-06-19

申请号：US11758632

申请日：2007-06-05

Applicant: Chien-Li Kuo ,  Ping-Chang Wu ,  Jui-Meng Jao ,  Hui-Ling Chen ,  Kai-Kuang Ho ,  Ching-Li Yang

Inventor： Chien-Li Kuo ,  Ping-Chang Wu ,  Jui-Meng Jao ,  Hui-Ling Chen ,  Kai-Kuang Ho ,  Ching-Li Yang

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L23/562 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract translation: 半导体晶片包括多个管芯区域，至少第一划线区域和围绕每个管芯区域的至少第二划线区域，至少位于第一划线区域中的第一金属结构，以及至少第二金属 结构位于第二划线区域。 第一金属结构包括平行于第一划线区域的至少第一槽，或包括以阵列布置的多个开口。 第二金属结构包括平行于第二划线区域的至少第二槽，或包括以阵列布置的多个开口。

公开(公告)号：US20080142606A1

公开(公告)日：2008-06-19

申请号：US11612480

申请日：2006-12-19

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: G06K19/06

CPC classification number: G06K19/06028 ,  G06K19/06046 ,  G06K19/067

Abstract: An invention relating to an eFuse bar code structure and a method of using the bar code structure is disclosed. The bar code structure includes a substrate and a plurality of eFuse elements disposed on the substrate and arranged in a form of an array, such that a bar pattern can be formed by the result of whether the fuse of the eFuse elements is blown or not. The method of using the bar code structure includes, with respect to a data, fuses of the eFuse elements in the bar code structure being correspondingly blown in accordance with an encoding method to form a bar pattern. The eFuse bar code structure according to the present invention can be manufactured by using a semiconductor manufacturing process, and thus it has small volume, a high density and may record a huge number of data.

Abstract translation: 公开了与eFuse条形码结构相关的发明和使用该条形码结构的方法。 条形码结构包括基板和多个eFuse元件，其设置在基板上并且以阵列的形式布置，使得可以通过eFuse元件的熔丝是否熔断来形成条形图案。 使用条形码结构的方法包括相对于数据，条形码结构中的eFuse元件的熔丝根据编码方法相应地被吹制以形成条形图案。 根据本发明的eFuse条形码结构可以通过使用半导体制造工艺制造，因此其体积小，密度高，并且可以记录大量的数据。

公开(公告)号：US20070235853A1

公开(公告)日：2007-10-11

申请号：US11399129

申请日：2006-04-05

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package structure including a substrate, a first chip and a second chip is provided. The first contacts and the second contacts of the substrate are respectively arranged to reside on a first side region and a second side region of the substrate. The first chip disposed on the substrate and has a plurality of first bonding pads arranged to reside on a first wire-bonding region of the first chip adjacent to the first contacts and are electrically connected to the first contacts via a plurality of first wires. The second chip is disposed on the first chip away from the symmetrical center of the first chip. The second chip has a plurality of second bonding pads arranged to reside on a second wire-bonding region of the second chip adjacent to the second contacts and are electrically connected to the second contacts via a plurality of second wires.

Abstract translation: 提供了包括基板，第一芯片和第二芯片的芯片封装结构。 衬底的第一触点和第二触点分别布置成位于衬底的第一侧区域和第二侧区域上。 所述第一芯片设置在所述基板上，并且具有布置成位于所述第一芯片的与所述第一触点相邻的第一引线接合区域上并且经由多个第一布线电连接到所述第一触点的多个第一焊盘。 第二芯片设置在远离第一芯片的对称中心的第一芯片上。 第二芯片具有多个第二接合焊盘，布置成位于与第二触点相邻的第二芯片的第二引线接合区域上，并且经由多个第二引线电连接到第二触点。

公开(公告)号：US20070102792A1

公开(公告)日：2007-05-10

申请号：US11308511

申请日：2006-03-31

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L23/544

CPC classification number: H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layer crack stop structure is described, disposed entirely in a die, entirely in a scribe line region outside the die, or partially in the die and partially in the scribe line region. The multi-layer crack stop structure is formed by stacking multiple layers of hollow crack stop units. The multi-layer crack stop structure can effectively prevent some damages like chipping, delamination or peeling-off from occurring to the active circuit region when the wafer is being sawn or when the die is subject to thermal cycles for testing, so that a better die can be obtained and the reliability of the packaged die can be significantly improved.

Abstract translation: 描述了多层裂纹停止结构，其完全设置在模具中，完全在模具外部的划线区域中，或者部分地设置在模具中，部分地设置在划线区域中。 多层裂缝停止结构通过堆叠多层中空裂缝停止单元形成。 多层裂纹停止结构可以有效地防止当晶片被锯切时或当模具经受热循环以进行测试时，有源电路区域发生切屑，分层或剥离等一些损坏，从而更好的模具 可以显着提高包装模具的可靠性。

公开(公告)号：US20130009656A1

公开(公告)日：2013-01-10

申请号：US13176721

申请日：2011-07-05

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: G01R31/00 ,  G01R1/067

CPC classification number: H01L22/34

Abstract: A test pad structure on a wafer includes at least a scribe line positioned on a wafer, a pad region defined in the scribe line, and a metal pad positioned in the pad region. An area of the metal pad and an area of the pad region include a ratio, and the ratio is lower than equal to 50%.

Abstract translation: 晶片上的测试焊盘结构至少包括位于晶片上的划线，限定在划线中的焊盘区域和位于焊盘区域中的金属焊盘。 金属焊盘的区域和焊盘区域的区域包括比率，该比率低于等于50％。

公开(公告)号：US20090294994A1

公开(公告)日：2009-12-03

申请号：US12129333

申请日：2008-05-29

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and the opening exposes a part of the bond pad. The part of the topmost metal layer located under the opening serves as a supporting layer. The supporting layer has at least a slot, and the topmost metal layer is electrically connected to the bond pad through a plurality of via plugs.

Abstract translation: 公开了一种位于有源电路结构之上的接合焊盘结构。 接合焊盘结构包括在有源电路结构中的接合焊盘，钝化层和最顶层的金属层。 钝化层覆盖接合焊盘，并且具有开口，并且开口露出接合焊盘的一部分。 位于开口下方的顶部金属层的一部分用作支撑层。 支撑层具有至少一个槽，并且最顶层的金属层通过多个通孔塞电连接到接合焊盘。

公开(公告)号：US20090283916A1

公开(公告)日：2009-11-19

申请号：US12119709

申请日：2008-05-13

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L23/538 ,  H01L21/00

CPC classification number: H01L25/50 ,  H01L22/22 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of reworking a chip includes providing a first chip and a second chip. The first and second chips have at least one first module and at least one second module, respectively. The first and second modules electrically connect with each other. The first module of the first chip has a defect. The second module of the second chip has a defect. The first module having a defect of the first chip is opened with the second module of the first chip, and the second module having a defect of the second chip is opened with the first module of the second chip. The first and second chips are stacked, and the second module of the first chip is electrically connects with the first module of the second chip.

Abstract translation: 芯片重做方法包括提供第一芯片和第二芯片。 第一和第二芯片分别具有至少一个第一模块和至少一个第二模块。 第一和第二模块彼此电连接。 第一个芯片的第一个模块有缺陷。 第二个芯片的第二个模块有缺陷。 具有第一芯片的缺陷的第一模块用第一芯片的第二模块打开，并且具有第二芯片的缺陷的第二模块用第二芯片的第一模块打开。 堆叠第一和第二芯片，第一芯片的第二模块与第二芯片的第一模块电连接。

公开(公告)号：US20090008782A1

公开(公告)日：2009-01-08

申请号：US11774388

申请日：2007-07-06

Applicant: Ping-Chang Wu

Inventor： Ping-Chang Wu

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a dielectric layer, a conductive structure, a low-k dielectric layer and a plug. The conductive structure is disposed in the dielectric layer, having a recess portion. The low-k dielectric layer is disposed on the dielectric layer. The plug is disposed in the low-k dielectric layer and has a protruding bonding portion on the bottom of the plug. The bonding portion is extended into the dielectric layer and connected to the recess portion of the conductive structure.

Abstract translation: 提供集成电路结构。 集成电路结构包括电介质层，导电结构，低k电介质层和插塞。 导电结构设置在电介质层中，具有凹部。 低介电常数介质层设置在电介质层上。 插头设置在低k电介质层中，并且在插头的底部上具有突出的接合部分。 接合部分延伸到电介质层中并连接到导电结构的凹部。