公开(公告)号：US07392366B2

公开(公告)日：2008-06-24

申请号：US11228781

申请日：2005-09-16

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard J. Eickemeyer ,  Lee E. Eisen ,  Philip G. Emma ,  John B. Griswell ,  Zhigang Hu ,  Hung Q. Le ,  Douglas R. Logan ,  Balaram Sinharoy

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard J. Eickemeyer ,  Lee E. Eisen ,  Philip G. Emma ,  John B. Griswell ,  Zhigang Hu ,  Hung Q. Le ,  Douglas R. Logan ,  Balaram Sinharoy

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3867

摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.

摘要翻译： 多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。 监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。 对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。 此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。 因此，处理器避免浪费电力不必要的或放置保持器提取。

公开(公告)号：US20110283095A1

公开(公告)日：2011-11-17

申请号：US12778192

申请日：2010-05-12

申请人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

发明人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30149 ,  G06F9/30189

摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

摘要翻译： 提供了将工作负载从主线程卸载到辅助线程的机制。 机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。 分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。 硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。 如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。 此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

公开(公告)号：US08423750B2

公开(公告)日：2013-04-16

申请号：US12778192

申请日：2010-05-12

申请人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

发明人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

IPC分类号： G06F9/48

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30149 ,  G06F9/30189

摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

公开(公告)号：US20080263331A1

公开(公告)日：2008-10-23

申请号：US11736855

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/384

摘要： A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance.

摘要翻译： 通用寄存器重命名机制，用于使用公共目标标签的多个目标的指令。 对于更新多个目的地的每个指令，分配单个重命名条目来处理与其相关联的所有目的地。 现在，一个重命名条目由一个DTAG和一个向量组成，用于指示由这样的特定指令更新的目标的类型。 例如，可以将普通DTAG分配给更新通用寄存器（GPR），定点异常寄存器（XER）和条件码寄存器（CR）目的地的固定点单元指令（FXU）。 在冲洗时间期间，恢复链路中的DTAG可以用于恢复指示最年轻的指令更新特定架构的寄存器的信息。 通过为所有类型的目的地使用单一的通用重命名结构，可以实现大量的硅和电源节省，而不需要牺牲性能。

公开(公告)号：US20080263321A1

公开(公告)日：2008-10-23

申请号：US11736844

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F15/00

CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

摘要： A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types.

摘要翻译： 在微处理器中提供了用于不同指令类型的目标的统一寄存器重命名机制。 通用重命名机制使用单个重命名结构重命名不同指令​​类型的目标。 因此，更新浮点寄存器（FPR）的指令可以与使用相同的重命名结构更新通用寄存器（GPR）或向量多媒体扩展（VMX）指令寄存器（VR））的指令一起重命名，因为 GPR的架构状态数量与FPR和VR的架构状态数量相同。 每个目的地标签（DTAG）被分配到一个目的地。 可将浮点指令分配给DTAG，然后将固定点指令分配给下一个DTAG等等。 使用通用重命名机制，可以通过为所有指令类型只有一个重命名结构来节省显着的硅和功率。

公开(公告)号：US07765384B2

公开(公告)日：2010-07-27

申请号：US11736844

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

摘要： A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types.

摘要翻译： 在微处理器中提供了用于不同指令类型的目标的统一寄存器重命名机制。 通用重命名机制使用单个重命名结构重命名不同指令​​类型的目标。 因此，更新浮点寄存器（FPR）的指令可以与使用相同的重命名结构更新通用寄存器（GPR）或向量多媒体扩展（VMX）指令寄存器（VR））的指令一起重命名，因为 GPR的架构状态数量与FPR和VR的架构状态数量相同。 每个目的地标签（DTAG）被分配到一个目的地。 可将浮点指令分配给DTAG，然后将固定点指令分配给下一个DTAG等等。 使用通用重命名机制，可以通过为所有指令类型只有一个重命名结构来节省显着的硅和功率。

公开(公告)号：US09037837B2

公开(公告)日：2015-05-19

申请号：US13438087

申请日：2012-04-03

申请人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

发明人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30149 ,  G06F9/30189

摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

摘要翻译： 提供了将工作负载从主线程卸载到辅助线程的机制。 机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。 分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。 硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。 如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。 此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

公开(公告)号：US20120254594A1

公开(公告)日：2012-10-04

申请号：US13438087

申请日：2012-04-03

申请人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

发明人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30149 ,  G06F9/30189

摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

摘要翻译： 提供了将工作负载从主线程卸载到辅助线程的机制。 机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。 分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。 硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。 如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。 此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

公开(公告)号：US07809929B2

公开(公告)日：2010-10-05

申请号：US11736855

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/384

摘要： A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance.

摘要翻译： 通用寄存器重命名机制，用于使用公共目标标签的多个目标的指令。 对于更新多个目的地的每个指令，分配单个重命名条目来处理与其相关联的所有目的地。 现在，一个重命名条目由一个DTAG和一个向量组成，用于指示由这样的特定指令更新的目标的类型。 例如，可以将普通DTAG分配给更新通用寄存器（GPR），定点异常寄存器（XER）和条件码寄存器（CR）目的地的固定点单元指令（FXU）。 在冲洗时间期间，恢复链路中的DTAG可以用于恢复指示最年轻的指令更新特定架构的寄存器的信息。 通过为所有类型的目的地使用单一的通用重命名结构，可以实现大量的硅和电源节省，而不需要牺牲性能。

公开(公告)号：US09086986B2

公开(公告)日：2015-07-21

申请号：US13606743

申请日：2012-09-07

申请人： Harold W. Cain, III ,  Hung Q. Le ,  Bryan Lloyd ,  Shih-Hsiung Tung

发明人： Harold W. Cain, III ,  Hung Q. Le ,  Bryan Lloyd ,  Shih-Hsiung Tung

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

摘要： There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.

摘要翻译： 提供了一种用于检测事务和事务存储器中的TLB（翻译后备缓冲器）冲突之间的冲突的方法，其中处理器接收到TLB击倒操作消息以使处理器的TLB中的至少一个条目相应对应 至少一页。 处理器跟踪事务触摸的页面。 处理器确定接收的TLB拍摄操作消息是否与所触摸的页面中的一个相关联。 响应于确定接收到的TLB击倒操作消息与所触摸的页面之一相关联，处理器中止该事务。