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1.发明申请公开(公告)号：US20180365162A1
公开(公告)日：2018-12-20
申请号：US15625444
申请日：2017-06-16
发明人： Uwe Brandt , Ute Gaertner , Lisa C. Heller , Markus Helms , Thomas Köhler , Frank Lehnert , Jennifer A. Navarro , Rebecca S. Wisniewski
IPC分类号： G06F12/1027 , G06F12/1009
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/30 , G06F2212/50 , G06F2212/65 , G06F2212/68 , G06F2212/682
摘要： Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.
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公开(公告)号：US20180088868A1
公开(公告)日：2018-03-29
申请号：US15811722
申请日：2017-11-14
发明人： ROBERT MILLER, JR. , HARRIS M. MORGENSTERN , JAMES H. MULDER , ELPIDA TZORTZATOS , DIETER WELLERDIEK
IPC分类号： G06F3/06 , G06F12/1027 , G06F12/02
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0685 , G06F12/023 , G06F12/1009 , G06F12/1027 , G06F2212/1016 , G06F2212/1041 , G06F2212/152 , G06F2212/657 , G06F2212/682 , G06F2212/683
摘要： Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.
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公开(公告)号：US09921895B2
公开(公告)日：2018-03-20
申请号：US15275790
申请日：2016-09-26
IPC分类号： G06F11/00 , G06F12/10 , G06F3/06 , G06F9/46 , G06F9/30 , G06F12/0831 , G06F12/1027 , G06F9/38
CPC分类号： G06F11/004 , G06F3/0619 , G06F3/0653 , G06F3/0674 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/30189 , G06F9/3834 , G06F9/3859 , G06F9/467 , G06F12/0833 , G06F12/1027 , G06F2212/621 , G06F2212/682
摘要： Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
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公开(公告)号：US20170293567A1
公开(公告)日：2017-10-12
申请号：US15632654
申请日：2017-06-26
申请人： ARM LIMITED
发明人： Richard F. BRYANT , Kim Richard SCHUTTENBERG , Lilian Atieno HUTCHINS , Thomas Edward ROBERTS , Alex James WAUGH , Max John BATLEY
IPC分类号： G06F12/1027 , G06F12/1036 , G06F9/30 , G06F12/1009 , G06F9/46
CPC分类号： G06F12/1027 , G06F9/30043 , G06F9/467 , G06F12/0815 , G06F12/0831 , G06F12/1009 , G06F12/1036 , G06F2212/1008 , G06F2212/1016 , G06F2212/1021 , G06F2212/50 , G06F2212/65 , G06F2212/68 , G06F2212/682
摘要： An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.
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公开(公告)号：US09785557B1
公开(公告)日：2017-10-10
申请号：US15333833
申请日：2016-10-25
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/0837 , G06F12/0808 , G06F12/0811 , G06F12/0842 , G06F12/0891 , G06F12/1027 , G06F12/12
CPC分类号： G06F12/0837 , G06F12/0808 , G06F12/0811 , G06F12/0842 , G06F12/0891 , G06F12/1027 , G06F12/1036 , G06F12/12 , G06F2212/1016 , G06F2212/1032 , G06F2212/6042 , G06F2212/682 , G06F2212/683
摘要： In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.
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公开(公告)号：US20170286316A1
公开(公告)日：2017-10-05
申请号：US15089211
申请日：2016-04-01
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1009 , G06F2212/682
摘要： An apparatus and method are described for managing TLB coherence. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; one or more epoch counters each programmed with a specified epoch value; and TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value.
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公开(公告)号：US20170286315A1
公开(公告)日：2017-10-05
申请号：US15088302
申请日：2016-04-01
申请人： Cavium, Inc.
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/0811 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/1044 , G06F2212/152 , G06F2212/452 , G06F2212/651 , G06F2212/682 , G06F2212/683
摘要： Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).
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公开(公告)号：US09772945B1
公开(公告)日：2017-09-26
申请号：US15333873
申请日：2016-10-25
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/0837 , G06F12/0808 , G06F12/0811 , G06F12/0842 , G06F12/0891 , G06F12/1027 , G06F12/12
CPC分类号： G06F12/0837 , G06F9/52 , G06F12/0808 , G06F12/0811 , G06F12/0833 , G06F12/0842 , G06F12/0891 , G06F12/1027 , G06F12/12 , G06F2212/1024 , G06F2212/1032 , G06F2212/6042 , G06F2212/682 , G06F2212/683
摘要： In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address. Subsequent memory referent instructions can be ordered with respect to the broadcast synchronization request by a synchronization instruction.
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公开(公告)号：US09747241B2
公开(公告)日：2017-08-29
申请号：US15453179
申请日：2017-03-08
申请人： Google Inc.
发明人： Benjamin C. Serebrin
CPC分类号： G06F13/4022 , G06F3/0611 , G06F3/0656 , G06F3/067 , G06F12/0813 , G06F12/0882 , G06F12/10 , G06F12/1036 , G06F12/1045 , G06F12/1081 , G06F12/109 , G06F12/1425 , G06F2212/1016 , G06F2212/1024 , G06F2212/1044 , G06F2212/1048 , G06F2212/152 , G06F2212/154 , G06F2212/264 , G06F2212/604 , G06F2212/608 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/682 , G06F2212/683
摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing an address in a memory of a switch. One of the systems includes a switch that receives packets from and delivers packets to devices connected to a bus without any components on the bus between the switch and each of the devices, a memory integrated into the switch to store a mapping of virtual addresses to physical addresses, and a storage medium integrated into the switch storing instructions executable by the switch to cause the switch to perform operations including receiving a response to an address translation request for a device connected to the switch by the bus, the response including a mapping of a virtual address to a physical address, and storing, in the memory, the mapping of the virtual address to the physical address in response to receiving the response.
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公开(公告)号：US09697135B2
公开(公告)日：2017-07-04
申请号：US15145585
申请日：2016-05-03
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F12/1009 , G06F12/1027
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/682
摘要： A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.
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