公开(公告)号：US20190043411A1

公开(公告)日：2019-02-07

申请号：US15863396

申请日：2018-01-05

申请人： Prashant D. Chaudhari ,  Michael N. Derr ,  Paul Diefenbaugh ,  Sameer Kalathil Perazhi ,  Fong-Shek Lam ,  Arthur Jeremy Runyan ,  Jason Tanner

发明人： Prashant D. Chaudhari ,  Michael N. Derr ,  Paul Diefenbaugh ,  Sameer Kalathil Perazhi ,  Fong-Shek Lam ,  Arthur Jeremy Runyan ,  Jason Tanner

IPC分类号： G09G3/20 ,  G06T1/60 ,  G06F3/14 ,  G06T9/00

摘要： Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

公开(公告)号：US5555510A

公开(公告)日：1996-09-10

申请号：US284185

申请日：1994-08-02

申请人： Jerry Verseput ,  Fong-Shek Lam ,  Prasanna Shah

发明人： Jerry Verseput ,  Fong-Shek Lam ,  Prasanna Shah

IPC分类号： G06F11/20 ,  G06F13/40 ,  H02H9/00

CPC分类号： H02H9/004 ,  G06F13/4072 ,  Y10T307/461

摘要： A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state. Next, detect that the PC card has been completely inserted or removed by monitoring the ground pins or the card detect signal pins. Next, apply power to the PCMCIA card socket. After a delay return the common address, data and control lines to their normal operating impedance level.

摘要翻译： 一种适用于具有连接到CPU的系统总线的主机系统的方法和具有状态寄存器的PCMCIA控制器，用于向CPU发送信号的装置和能够处于正常和高阻抗状态的行缓冲器的装置。 多针连接器位于每个卡插槽中，并连接到线路缓冲器。 每个连接器具有公共地址，数据和控制引脚，电源引脚，接地引脚长于数据引脚，并且卡检测信号引脚短于信号引脚。 第一步是通过监测地面和卡检测信号引脚来检测PCMCIA卡插入或取出插座的开始。 检测后，通过断言退出信号，开始终止公共地址，数据和控制线的所有CPU使用。 接下来，通过监视控制器中的状态寄存器来确定是否终止使用。 接下来，将公共地址，数据和控制线置于高阻态。 接下来，通过监视接地引脚或卡检测信号引脚来检测PC卡是否完全插入或取出。 接下来，为PCMCIA卡插座供电。 经过延时后，公共地址，数据和控制线路恢复正常的工作阻抗级别。

公开(公告)号：US06999089B1

公开(公告)日：2006-02-14

申请号：US09539637

申请日：2000-03-30

申请人： Fong-Shek Lam ,  Kim A. Meinerth

发明人： Fong-Shek Lam ,  Kim A. Meinerth

IPC分类号： G09G5/397

CPC分类号： G09G5/395 ,  G09G5/14 ,  G09G2340/045 ,  G09G2340/125

摘要： An overlay video processing system provides an early start to pixel processing for the next overlay scan line. The overlay processor begins processing the next overlay scan line while still displaying the current scan line. A FIFO buffer is used to provide the overlay video data to the display. When the buffer provides a predetermined amount of data to the current overlay scan line, the buffer begins to load the data for the next overlay scan line. In one embodiment, the buffer may begin loading data for the next overlay scan line when approximately half the current overlay scan line is displayed.

摘要翻译： 覆盖视频处理系统为下一个叠加扫描线提供了早期的像素处理开始。 覆盖处理器开始处理下一个叠加扫描线，同时仍显示当前的扫描线。 FIFO缓冲器用于向显示器提供覆盖视频数据。 当缓冲器向当前覆盖扫描线提供预定量的数据时，缓冲器开始加载下一叠加扫描线的数据。 在一个实施例中，当显示当前叠加扫描线的大约一半时，缓冲器可以开始为下一叠加扫描线加载数据。

公开(公告)号：US06625708B1

公开(公告)日：2003-09-23

申请号：US09447536

申请日：1999-11-23

申请人： Fong-Shek Lam

发明人： Fong-Shek Lam

IPC分类号： G06F1200

CPC分类号： G06T1/60

摘要： A method and apparatus of defining a line buffer configuration in a memory is disclosed. In one embodiment, the method and apparatus receives input data information and mode information, proceeds to select a type of the line buffer configuration according to the mode information, and dynamically generates addresses for the selected type of line buffer configuration in the memory according to the input data information.

摘要翻译： 公开了一种在存储器中定义行缓冲器配置的方法和装置。 在一个实施例中，该方法和装置接收输入数据信息和模式信息，继续根据模式信息选择一行类型的行缓冲器配置，并根据该方式动态地生成存储器中所选类型的行缓冲器配置的地址 输入数据信息。