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    Unified multi-transport medium connector architecture
    1.
    发明申请
    Unified multi-transport medium connector architecture 有权
    统一的多传输媒体连接器架构

    公开(公告)号：US20100049885A1

    公开(公告)日：2010-02-25

    申请号：US12229453

    申请日：2008-08-22

    申请人： Prashant R. Chandra ,  Ajay V. Bhatt ,  Kevin Kahn ,  Steve McGowan

    发明人： Prashant R. Chandra ,  Ajay V. Bhatt ,  Kevin Kahn ,  Steve McGowan

    IPC分类号： G06F3/00

    CPC分类号： G06F13/122 ,  H04L45/62 ,  H04L47/2491 ,  H04Q11/0062 ,  H04Q11/0066

    摘要： A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal.

    摘要翻译： 公开了一种装置，方法和系统。 在一个实施例中，设备包括路由器，用于在多个主机控制器与一个或多个外围设备之间传输数据分组。 路由器可以从主机控制器接收数据包，并通过数据传输路径将数据包发送到外围设备。 外围设备通过第一通用多传输介质（UMTM）连接器耦合到第一数据传输路径。 连接器包括能够传送光信号内的第一数据分组的光耦合器和能够在电信号内传输第一数据分组的电耦合。

    Method and apparatus for providing event handling functionality in a computer system
    3.
    发明授权
    Method and apparatus for providing event handling functionality in a computer system 有权
    用于在计算机系统中提供事件处理功能的方法和装置

    公开(公告)号：US06408386B1

    公开(公告)日：2002-06-18

    申请号：US09770970

    申请日：2001-01-25

    申请人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    发明人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    IPC分类号： G06F940

    CPC分类号： G06F9/4812 ,  G06F9/30181 ,  G06F9/3822

    摘要： Method And Apparatus for Providing Event Handling Functionality in a Computer System. According to one embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

    摘要翻译： 在计算机系统中提供事件处理功能的方法和装置。 根据本发明的一个实施例，计算机系统包括处理器中的指令集单元和事件处理单元，以及包括第一事件处理程序的第一多个事件处理程序。 指令集单元支持第一和第二指令集。 在处理来自第一和第二单元的指令期间出现的问题是使处理器执行第一组多个事件处理程序中适当的一个。 第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。 所有第二组事件都映射到第一个事件处理程序。

    Article for providing event handling functionality in a processor supporting different instruction sets
    5.
    发明授权
    Article for providing event handling functionality in a processor supporting different instruction sets 有权
    用于在支持不同指令集的处理器中提供事件处理功能的文章

    公开(公告)号：US06584558B2

    公开(公告)日：2003-06-24

    申请号：US10132554

    申请日：2002-04-24

    申请人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    发明人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    IPC分类号： G06F940

    CPC分类号： G06F9/4812 ,  G06F9/30181 ,  G06F9/3822

    摘要： An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

    摘要翻译： 描述了表示提供事件处理功能的处理器的文章。 根据本发明的一个实施例，该物品包括存储表示包括指令集单元和事件处理单元的处理器的数据的机器可读介质，以及包括第一事件处理程序的第一多个事件处理程序。 指令集单元支持第一和第二指令集。 在处理来自第一和第二单元的指令期间出现的问题是使物品执行第一多个事件处理程序中适当的一个。 第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。 所有第二组事件都映射到第一个事件处理程序。

    Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture
    6.
    发明授权
    Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture 失效
    地址转换/旁路中间分段转换以适应两种不同的指令集架构

    公开(公告)号：US06219774B1

    公开(公告)日：2001-04-17

    申请号：US09048241

    申请日：1998-03-25

    申请人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    发明人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    IPC分类号： G06F1210

    CPC分类号： G06F9/4812 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3822

    摘要： A Method and Apparatus for Providing Memory Management and Event Handling Functionality in a Computer System. According to one embodiment of the invention, a processor comprises an instruction set unit, a segmentation unit, and a paging unit. The instruction set unit is to support a first and second instruction sets. The segmentation unit is coupled to the instruction set unit to translate virtual addresses used by the first instruction set into translated addresses. The paging unit is coupled to the instruction set unit to translate both virtual addresses used by the second instruction set and the translated addresses into physical addresses. According to another embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second instruction sets respectively causes a first and second set of events. The event handling unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

    摘要翻译： 一种用于在计算机系统中提供存储器管理和事件处理功能的方法和装置。 根据本发明的一个实施例，处理器包括指令集单元，分割单元和寻呼单元。 指令集单元支持第一和第二指令集。 分割单元耦合到指令集单元以将由第一指令集使用的虚拟地址转换为转换的地址。 寻呼单元耦合到指令集单元以将由第二指令集使用的两个虚拟地址和转换的地址转换成物理地址。 根据本发明的另一实施例，计算机系统包括处理器中的指令集单元和事件处理单元，以及包括第一事件处理程序的第一多个事件处理程序。 指令集单元支持第一和第二指令集。 在处理来自第一和第二指令集的指令期间出现的问题分别导致第一和第二组事件。 事件处理单元是使处理器执行第一组多个事件处理程序中适当的一个。 第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。 所有第二组事件都映射到第一个事件处理程序。

    Method and apparatus for providing two system architectures in a processor
    7.
    发明授权
    Method and apparatus for providing two system architectures in a processor 失效
    用于在处理器中提供两个系统架构的方法和装置

    公开(公告)号：US5774686A

    公开(公告)日：1998-06-30

    申请号：US482239

    申请日：1995-06-07

    申请人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    发明人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

    IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/48 ,  G06F9/30

    CPC分类号： G06F9/4812 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3822

    摘要： A processor having two system configurations is provided. The apparatus generally includes an instruction set unit, a system unit, an internal bus, and a bus unit. The instruction set unit, the system unit, and the bus unit are coupled together by the internal bus. The system unit is capable of selectively operating in one of two system configurations. The first system configuration provides a first system architecture, while the second system configuration provides a second system architecture. The bus unit is used for sending and receiving signals from the instruction set unit and the system unit. According to another aspect of the invention, the instruction set unit is capable of selectively operating in one of two instruction set configurations. The first instruction set configuration provides for the execution of instruction belonging to a first instruction set, while the second instruction set configuration provides for the execution of instructions belonging to a second instruction set.

    摘要翻译： 提供具有两个系统配置的处理器。 该装置通常包括指令集单元，系统单元，内部总线和总线单元。 指令集单元，系统单元和总线单元通过内部总线耦合在一起。 系统单元能够选择性地在两种系统配置之一中操作。 第一系统配置提供第一系统架构，而第二系统配置提供第二系统架构。 总线单元用于从指令集单元和系统单元发送和接收信号。 根据本发明的另一方面，指令集单元能够选择性地以两种指令集配置中的一种进行操作。 第一指令集配置提供执行属于第一指令集的指令，而第二指令集配置提供属于第二指令集的指令的执行。

    Static and dynamic scheduling in an asynchronous transfer mode communication network
    8.
    发明授权
    Static and dynamic scheduling in an asynchronous transfer mode communication network 失效
    异步传输模式通信网络中的静态和动态调度

    公开(公告)号：US5619502A

    公开(公告)日：1997-04-08

    申请号：US307925

    申请日：1994-09-16

    申请人： Kevin Kahn ,  David Eckhardt

    发明人： Kevin Kahn ,  David Eckhardt

    IPC分类号： H04L12/56 ,  H04Q11/04

    CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5679

    摘要： A communication subsystem is disclosed including a static scheduler and a dynamic scheduler. The static scheduler accesses a scheduling list that specifies either a virtual circuit or a dynamic scheduling indication for each cell slot on a communication link. The static scheduler selects the virtual circuit specified by the scheduling list if the scheduling list specifies the virtual circuit for the cell slot and the dynamic scheduler selects a virtual circuit from a dynamic scheduling list for transfer of the outbound communication cell if the scheduling list specifies the dynamic scheduling indication for the cell slot. The communication subsystem also includes a counter that counts if an idle communication cell is transferred over the communication link due to an underrun such that the virtual circuit specified by the dynamic scheduling list is skipped if the counter indicates the underrun.

    摘要翻译： 公开了一种通信子系统，其包括静态调度器和动态调度器。 静态调度器访问指定通信链路上的每个小区时隙的虚拟电路或动态调度指示的调度列表。 如果调度列表指定了小区时隙的虚拟电路，则静态调度器选择由调度列表指定的虚拟电路，并且如果调度列表指定了出站通信小区，则动态调度器从动态调度列表中选择虚拟电路来传送出站通信小区 小区时隙的动态调度指示。 通信子系统还包括计数器，其计数如果空闲通信小区由于欠载而在通信链路上传送，使得如果计数器指示欠载，则跳过由动态调度列表指定的虚拟电路。