公开(公告)号：US06584558B2

公开(公告)日：2003-06-24

申请号：US10132554

申请日：2002-04-24

申请人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

发明人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

IPC分类号： G06F940

CPC分类号： G06F9/4812 ,  G06F9/30181 ,  G06F9/3822

摘要： An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

摘要翻译： 描述了表示提供事件处理功能的处理器的文章。 根据本发明的一个实施例，该物品包括存储表示包括指令集单元和事件处理单元的处理器的数据的机器可读介质，以及包括第一事件处理程序的第一多个事件处理程序。 指令集单元支持第一和第二指令集。 在处理来自第一和第二单元的指令期间出现的问题是使物品执行第一多个事件处理程序中适当的一个。 第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。 所有第二组事件都映射到第一个事件处理程序。

公开(公告)号：US06219774B1

公开(公告)日：2001-04-17

申请号：US09048241

申请日：1998-03-25

申请人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

发明人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

IPC分类号： G06F1210

CPC分类号： G06F9/4812 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3822

摘要： A Method and Apparatus for Providing Memory Management and Event Handling Functionality in a Computer System. According to one embodiment of the invention, a processor comprises an instruction set unit, a segmentation unit, and a paging unit. The instruction set unit is to support a first and second instruction sets. The segmentation unit is coupled to the instruction set unit to translate virtual addresses used by the first instruction set into translated addresses. The paging unit is coupled to the instruction set unit to translate both virtual addresses used by the second instruction set and the translated addresses into physical addresses. According to another embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second instruction sets respectively causes a first and second set of events. The event handling unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

摘要翻译： 一种用于在计算机系统中提供存储器管理和事件处理功能的方法和装置。 根据本发明的一个实施例，处理器包括指令集单元，分割单元和寻呼单元。 指令集单元支持第一和第二指令集。 分割单元耦合到指令集单元以将由第一指令集使用的虚拟地址转换为转换的地址。 寻呼单元耦合到指令集单元以将由第二指令集使用的两个虚拟地址和转换的地址转换成物理地址。 根据本发明的另一实施例，计算机系统包括处理器中的指令集单元和事件处理单元，以及包括第一事件处理程序的第一多个事件处理程序。 指令集单元支持第一和第二指令集。 在处理来自第一和第二指令集的指令期间出现的问题分别导致第一和第二组事件。 事件处理单元是使处理器执行第一组多个事件处理程序中适当的一个。 第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。 所有第二组事件都映射到第一个事件处理程序。

公开(公告)号：US5991874A

公开(公告)日：1999-11-23

申请号：US660094

申请日：1996-06-06

申请人： Jack D. Mills ,  Donald Alpert

发明人： Jack D. Mills ,  Donald Alpert

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/38 ,  G06F7/00 ,  G06F7/38

CPC分类号： G06F9/30032 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/384

摘要： An apparatus for use in a computer system comprises a first storage area and a circuit, coupled to the first storage area, configured to perform a comparison of a data element A with a data element B. In response to a single instruction, the circuit performs the comparison and outputs a condition field of at least one bits when the comparison of A and B is TRUE, or else the circuit outputs the ones-complement of the condition field when the comparison of A and B is FALSE. The circuit may be used in conjunction with a sequence of instructions to select bits from a first data element and bits from a second data element using the one or more condition field bits.

摘要翻译： 一种在计算机系统中使用的装置包括耦合到第一存储区域的第一存储区域和电路，被配置为执行数据元素A与数据元素B的比较。响应于单个指令，电路执行 当A和B的比较为TRUE时，比较并输出至少一个比特的条件字段，否则当A和B的比较为FALSE时，电路输出条件字段的补码。 电路可以与指令序列一起使用，以使用一个或多个条件字段位来从第一数据元素选择位和来自第二数据元素的位。

公开(公告)号：US06408386B1

公开(公告)日：2002-06-18

申请号：US09770970

申请日：2001-01-25

申请人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

发明人： Gary Hammond ,  Donald Alpert ,  Kevin Kahn ,  Harsh Sharangpani

IPC分类号： G06F940

CPC分类号： G06F9/4812 ,  G06F9/30181 ,  G06F9/3822

摘要： Method And Apparatus for Providing Event Handling Functionality in a Computer System. According to one embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

摘要翻译： 在计算机系统中提供事件处理功能的方法和装置。 根据本发明的一个实施例，计算机系统包括处理器中的指令集单元和事件处理单元，以及包括第一事件处理程序的第一多个事件处理程序。 指令集单元支持第一和第二指令集。 在处理来自第一和第二单元的指令期间出现的问题是使处理器执行第一组多个事件处理程序中适当的一个。 第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。 所有第二组事件都映射到第一个事件处理程序。

公开(公告)号：US06052801A

公开(公告)日：2000-04-18

申请号：US438474

申请日：1995-05-10

申请人： Gary N. Hammond ,  Donald Alpert

发明人： Gary N. Hammond ,  Donald Alpert

IPC分类号： G06F11/36 ,  G06F11/30 ,  G06F12/00

CPC分类号： G06F11/3648

摘要： A method and apparatus for providing breakpoints on a selectable address range. The apparatus generally includes a processor including a first storage area, a second storage area, a circuit and an execution unit. The first storage area has stored therein a first address, while the second storage area has stored therein a mask. The first address and the mask define an address range. In response to receiving a second address, the circuit accesses the first address stored in the first storage area and the mask stored in the second storage area. The circuit transmits a signal to cause a debug event if the second address is within the address range defined by the first address and the mask.

摘要翻译： 一种用于在可选地址范围上提供断点的方法和装置。 该装置通常包括处理器，该处理器包括第一存储区域，第二存储区域，电路和执行单元。 第一存储区域已经存储有第一地址，而第二存储区域已经存储有掩模。 第一个地址和掩码定义一个地址范围。 响应于接收到第二地址，电路访问存储在第一存储区域中的第一地址和存储在第二存储区域中的掩码。 如果第二地址在由第一地址和掩码定义的地址范围内，则电路发送信号以引起调试事件。

公开(公告)号：US5729724A

公开(公告)日：1998-03-17

申请号：US580035

申请日：1995-12-20

申请人： Harshvardhan Sharangpani ,  Donald Alpert ,  Hans Mulder

发明人： Harshvardhan Sharangpani ,  Donald Alpert ,  Hans Mulder

IPC分类号： G06F5/00 ,  G06F9/302 ,  G06F9/312 ,  G06F7/00

CPC分类号： G06F9/30014 ,  G06F5/00 ,  G06F9/30036 ,  G06F9/30043

摘要： A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.

摘要翻译： 一种用于提供自适应128位加载和存储操作的技术，以支持128位四重精度格式的计算的架构扩展，其中单个加载和存储指令集可在80位和128位上进行保存和恢复操作 位浮点寄存器文件。 128位加载和存储指令用于移动存储器中128位对齐的值。 传输需要128位存储器边界和浮点寄存器文件之间的数据移动，用于寄存器保存和恢复操作。 在一个实施例中，使用80位寄存器，在第二实施例中使用128位寄存器。 相同的指令在80位和128位寄存器上运行，将给定寄存器的内容映射到存储器中的128位边界字段。 加载/存储单元分配位定位，使得当使用80位寄存器时，80位移动到128位边界字段的最高位位置。 剩余的位位置用0填充。 当值移动到存储器时，执行相反的操作。

公开(公告)号：US20050091480A1

公开(公告)日：2005-04-28

申请号：US10982217

申请日：2004-11-05

申请人： John Crawford ,  Donald Alpert

发明人： John Crawford ,  Donald Alpert

IPC分类号： G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48 ,  G06F7/38 ,  G06F9/00

CPC分类号： G06F9/4812 ,  G06F9/45533

摘要： A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

摘要翻译： 本文公开了一种计算机系统，其包括专门设计为在虚拟操作模式下操作的给定微处理器，其允许先前为先前设计的单个程序微处理器写入的软件程序在受特定设计的主机之下的受保护的，分页的多任务环境中执行 操作软件程序。 该系统还包括使用形成主机程序的一部分的仿真软件来执行软件中断（INTn）指令的装置，以便模拟这些指令将由较早的微处理器执行的方式。 作为对整个计算机系统的独特改进，INTn指令中的某些指令通过仿真软件执行，而其他指令则通过与给定的微处理器及其主机操作软件程序协作的先前编写的程序来执行。

公开(公告)号：US5764959A

公开(公告)日：1998-06-09

申请号：US580069

申请日：1995-12-20

申请人： Harshvardhan Sharangpani ,  Donald Alpert ,  Hans Mulder

发明人： Harshvardhan Sharangpani ,  Donald Alpert ,  Hans Mulder

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F5/00

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30112 ,  G06F9/3013

摘要： A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.

摘要翻译： 一种用于提供自适应128位加载和存储操作的技术，以支持128位四重精度格式的计算的架构扩展，其中单个加载和存储指令集可在80位和128位上进行保存和恢复操作 位浮点寄存器文件。 128位加载和存储指令用于移动存储器中128位对齐的值。 传输需要128位存储器边界和浮点寄存器文件之间的数据移动，用于寄存器保存和恢复操作。 在一个实施例中，使用80位寄存器，在第二实施例中使用128位寄存器。 相同的指令在80位和128位寄存器上运行，将给定寄存器的内容映射到存储器中的128位边界字段。 加载/存储单元分配位定位，使得当使用80位寄存器时，80位移动到128位边界字段的最高位位置。 剩余的位位置用0填充。 当值移动到存储器时，执行相反的操作。

公开(公告)号：US5740413A

公开(公告)日：1998-04-14

申请号：US899085

申请日：1997-07-23

申请人： Donald Alpert ,  Gary Hammond

发明人： Donald Alpert ,  Gary Hammond

IPC分类号： G06F11/36 ,  G06F11/30

CPC分类号： G06F11/3664

摘要： A method and apparatus for providing address breakpoints, branch breakpoints, and single stepping is described. According to one aspect of the invention, a processor is provided which generally includes an execution unit, a first storage area, and an address breakpoint unit. The execution unit recognizes a first debug event in response to the execution of an instruction which causes a branch to be taken. The first storage area has stored therein information. The address breakpoint unit is coupled to the first storage area to receive the information. The address breakpoint unit is also coupled to the execution unit to receive addresses. The address breakpoint unit determines whether the addresses it receives form the execution unit are identified by the information. The execution unit recognizes a second debug event when the address breakpoint unit indicates one of these addresses is identified by the information.

摘要翻译： 描述了一种用于提供地址断点，分支断点和单步进的方法和装置。 根据本发明的一个方面，提供一种处理器，其通常包括执行单元，第一存储区域和地址断点单元。 执行单元响应于执行导致分支的指令而识别第一调试事件。 第一存储区域中存储有信息。 地址断点单元耦合到第一存储区域以接收信息。 地址断点单元也耦合到执行单元以接收地址。 地址断点单元通过该信息确定其从执行单元接收的地址是否被识别。 当地址断点单元指示这些地址中的一个由信息识别时，执行单元识别第二调试事件。

公开(公告)号：US5671435A

公开(公告)日：1997-09-23

申请号：US496259

申请日：1995-06-28

申请人： Donald Alpert

发明人： Donald Alpert

IPC分类号： G06F15/78 ,  G06F1/00 ,  G06F9/30 ,  G06F9/445 ,  G06F11/00 ,  G06F21/00 ,  G06F11/30 ,  G06F12/06

CPC分类号： G06F21/73 ,  G06F11/006 ,  G06F9/30003 ,  G06F9/328 ,  G06F9/44505 ,  G06F2207/7219

摘要： A specialized set of read-only identification (ID) registers are used to store information relating to a microprocessor and its associated attributes, so that microcode is not needed to sequence through steps to obtain such processor identification. A software access a base ID (or identifier) register which includes family (type), model and step ID for the processor, as well as the number of "name" and "feature" registers present for conveying additional information pertaining to these attributes.

摘要翻译： 一组专用的只读标识（ID）寄存器用于存储与微处理器及其相关属性有关的信息，从而不需要通过步骤来获得这种处理器标识的微代码。 软件访问包括处理器的系列（类型），型号和步骤ID的基本ID（或标识符）寄存器，以及用于传送与这些属性有关的附加信息的“名称”和“特征”寄存器的数量。