公开(公告)号：US20130083047A1

公开(公告)日：2013-04-04

申请号：US13248996

申请日：2011-09-29

申请人： Prashant SHAMARAO ,  Rohit Singhal

发明人： Prashant SHAMARAO ,  Rohit Singhal

IPC分类号： G09G5/36

CPC分类号： G09G5/005 ,  G09G3/20 ,  G09G5/003 ,  G09G5/006 ,  G09G5/36 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/18

摘要： A system for buffering a video signal is provided. The system includes a graphics processing unit (GPU), the GPU generating the video signal, and a buffering circuit coupled to the GPU, the buffering circuit receiving and temporarily storing the video signal when the GPU enters a power saving mode. The system also includes a display device coupled to the bridge circuit and receiving the video signal from the buffering circuit. The buffering circuit includes an internal memory device configured to temporarily store a first portion of the video signal, and an external memory device configured to temporarily store a second portion of the video signal. A circuit and method for buffering a video signal are also provided.

摘要翻译： 提供了一种用于缓冲视频信号的系统。 该系统包括图形处理单元（GPU），产生视频信号的GPU以及耦合到GPU的缓冲电路，当GPU进入功率节省模式时，缓冲电路接收临时存储视频信号。 该系统还包括耦合到桥接电路并从缓冲电路接收视频信号的显示装置。 缓冲电路包括被配置为临时存储视频信号的第一部分的内部存储器件，以及被配置为临时存储视频信号的第二部分的外部存储器件。 还提供了用于缓冲​​视频信号的电路和方法。

公开(公告)号：US08686759B2

公开(公告)日：2014-04-01

申请号：US12712025

申请日：2010-02-24

申请人： Prashant Shamarao ,  Chris DeMarco ,  Rohit Singhal ,  Robert Bishop ,  Alex Reed

发明人： Prashant Shamarao ,  Chris DeMarco ,  Rohit Singhal ,  Robert Bishop ,  Alex Reed

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03F3/62

摘要： An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.

摘要翻译： AUX通道放大器，用于放大Display Port设备的AUX通道中的数据。 在一些实施例中，放大器包括耦合以放大从源极到信宿的信号的第一放大器和耦合到放大从信宿到信号源的信号的第二放大器。 切片机可以用来数字化来自信号源的信号。 在一些实施例中，时钟和数据恢复可用于从源接收信号，并且可以利用第二时钟和数据恢复来从信宿接收信号。 控制器确定数据流的方向，并相应地启用第一放大器或第二放大器。

公开(公告)号：US20110032006A1

公开(公告)日：2011-02-10

申请号：US12712025

申请日：2010-02-24

申请人： PRASHANT SHAMARAO ,  Chris Demarco ,  Rohit Singhal ,  Robert Bishop ,  Alex Reed

发明人： PRASHANT SHAMARAO ,  Chris Demarco ,  Rohit Singhal ,  Robert Bishop ,  Alex Reed

IPC分类号： H03B1/00

CPC分类号： H03F3/62

摘要： An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.

摘要翻译： AUX通道放大器，用于放大Display Port设备的AUX通道中的数据。 在一些实施例中，放大器包括耦合以放大从源极到信宿的信号的第一放大器和耦合到放大从信宿到信号源的信号的第二放大器。 切片机可以用来数字化来自信号源的信号。 在一些实施例中，时钟和数据恢复可用于从源接收信号，并且可以利用第二时钟和数据恢复来从信宿接收信号。 控制器确定数据流的方向，并相应地启用第一放大器或第二放大器。

公开(公告)号：US08212594B2

公开(公告)日：2012-07-03

申请号：US12854702

申请日：2010-08-11

申请人： Rohit Singhal ,  Chris DeMarco

发明人： Rohit Singhal ,  Chris DeMarco

IPC分类号： H03L7/00

CPC分类号： H04L7/0012 ,  G06F5/06

摘要： Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.

摘要翻译： 时域交叉系统和方法包括积分器，其在第一时钟域中累加多个时钟周期的输入采样以产生累积结果。 时域交叉电路在每次重复累积计数之后，在第一时钟域中对累积结果进行采样，以产生第一域积分。 第一域累积在时间延迟之后的第二时钟域中进行采样以产生第二域累积。 时间延迟确保第二时钟域相对于第一时钟域的适当建立和保持时间参数。 微分器通过延迟第二域积累并从第二域积累中减去延迟的第二域积累来在第二时钟域中产生输出信息。 当传输到第二时钟域作为输出信息时，系统和方法保留第一时钟域中的输入信息的时间特性。

公开(公告)号：US20120038398A1

公开(公告)日：2012-02-16

申请号：US12854702

申请日：2010-08-11

申请人： Rohit Singhal ,  Chris DeMarco

发明人： Rohit Singhal ,  Chris DeMarco

IPC分类号： H03L7/00

CPC分类号： H04L7/0012 ,  G06F5/06

摘要： Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.

摘要翻译： 时域交叉系统和方法包括积分器，其在第一时钟域中累加多个时钟周期的输入采样以产生累积结果。 时域交叉电路在每次重复累积计数之后，在第一时钟域中对累积结果进行采样，以产生第一域积分。 第一域累积在时间延迟之后的第二时钟域中进行采样以产生第二域累积。 时间延迟确保第二时钟域相对于第一时钟域的适当建立和保持时间参数。 微分器通过延迟第二域积累并从第二域积累中减去延迟的第二域积累来在第二时钟域中产生输出信息。 当传输到第二时钟域作为输出信息时，系统和方法保留第一时钟域中的输入信息的时间特性。