公开(公告)号：US11817400B2

公开(公告)日：2023-11-14

申请号：US17377131

申请日：2021-07-15

Applicant: Psiquantum, Corp.

Inventor： Yong Liang ,  Vimal Kumar Kamineni ,  Chia-Ming Chang ,  James McMahon

IPC: H01L23/00 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L23/562 ,  H01L21/02186 ,  H01L27/1203

Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.

公开(公告)号：US20240063146A1

公开(公告)日：2024-02-22

申请号：US18500504

申请日：2023-11-02

Applicant: Psiquantum, Corp.

Inventor： Yong Liang ,  Vimal Kumar Kamineni ,  Chia-Ming Chang ,  James McMahon

IPC: H01L23/00 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L23/562 ,  H01L21/02186 ,  H01L27/1203

Abstract: A wafer includes a silicon layer, a first dielectric layer on the silicon layer, and a ferroelectric layer on the first dielectric layer. The ferroelectric layer defines one or more gaps between portions of the ferroelectric layer. The wafer also includes a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps.

公开(公告)号：US20230018940A1

公开(公告)日：2023-01-19

申请号：US17377131

申请日：2021-07-15

Applicant: Psiquantum, Corp.

Inventor： Yong Liang ,  Vimal Kumar Kamineni ,  Chia-Ming Chang ,  James McMahon

IPC: H01L23/00 ,  H01L27/12 ,  H01L21/02

Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.