公开(公告)号：US11200363B1

公开(公告)日：2021-12-14

申请号：US16941315

申请日：2020-07-28

申请人： Pulsic Limited

发明人： Mark Waller ,  Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  G09G3/20

摘要： Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

公开(公告)号：US10783292B1

公开(公告)日：2020-09-22

申请号：US15162458

申请日：2016-05-23

申请人： Pulsic Limited

发明人： Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F17/50 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F111/12

摘要： An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

公开(公告)号：US10726184B1

公开(公告)日：2020-07-28

申请号：US15950112

申请日：2018-04-10

申请人： Pulsic Limited

发明人： Mark Waller ,  Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F17/50 ,  G06F30/392 ,  G06F30/39 ,  G06F30/394 ,  G09G3/20

摘要： Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

公开(公告)号：US12032893B2

公开(公告)日：2024-07-09

申请号：US17644320

申请日：2021-12-14

申请人： Pulsic Limited

发明人： Mark Waller ,  Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F30/394 ,  G06F30/39 ,  G06F30/392 ,  G09G3/20

CPC分类号： G06F30/392 ,  G06F30/39 ,  G06F30/394 ,  G09G3/2088

摘要： Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

公开(公告)号：US11748538B1

公开(公告)日：2023-09-05

申请号：US17655989

申请日：2022-03-22

申请人： Pulsic Limited

发明人： Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F30/327 ,  G06F30/394 ,  G06F30/392 ,  G06F17/00 ,  G06F111/12

CPC分类号： G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F2111/12

摘要： An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

公开(公告)号：US20220108059A1

公开(公告)日：2022-04-07

申请号：US17644320

申请日：2021-12-14

申请人： Pulsic Limited

发明人： Mark Waller ,  Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F30/392 ,  G06F30/39 ,  G06F30/394

摘要： Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

公开(公告)号：US11281828B1

公开(公告)日：2022-03-22

申请号：US17028937

申请日：2020-09-22

申请人： Pulsic Limited

发明人： Paul Clewes ,  Liang Gao ,  Jonathan Longrigg

IPC分类号： G06F30/327 ,  G06F30/394 ,  G06F30/392 ,  G06F111/12

摘要： An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.