公开(公告)号：US20160196231A1

公开(公告)日：2016-07-07

申请号：US14591749

申请日：2015-01-07

Applicant: QUALCOMM INCORPORATED

Inventor： NHON TOAI QUACH ,  JEAN-MARIE QUOC DANH TRAN ,  NIKOLAI SCHLEGEL ,  JEAN-LOUIS TARDIEUX ,  BING XIAO

IPC: G06F13/40 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F13/4068 ,  G06F11/3027 ,  G06F11/3409

Abstract: Various embodiments of methods and systems for managing bus bandwidth allocation in a system on a chip are disclosed. Certain embodiments monitor a high speed bus for a measurement window of time to identify valid bits uniquely associated with transaction requests issued by a master processing engine. The method continues to monitor the bus over the window to identify completed transactions. A latency value is calculated by subtracting a target latency from an actual latency for each completed transaction. The latency value is aggregated in a counter. At the conclusion of the window, if the aggregated latency value is positive, the method may conclude that the average latency per transaction over the window exceeded the target latency per transaction and that the bandwidth allocated to the engine should be increased.

Abstract translation: 公开了用于在芯片上的系统中管理总线带宽分配的方法和系统的各种实施例。 某些实施例监视高速总线用于测量时间窗口，以识别与由主处理引擎发出的事务请求唯一相关联的有效位。 该方法继续监视窗口上的总线以识别已完成的事务。 通过从每个完成的交易的实际延迟中减去目标等待时间来计算延迟值。 延迟值汇总在计数器中。 在窗口结束时，如果聚合延迟值为正，则该方法可以得出结论，窗口上每事务的平均延迟超过每个事务的目标延迟，并且应该增加分配给引擎的带宽。