公开(公告)号：US20160077959A1

公开(公告)日：2016-03-17

申请号：US14485555

申请日：2014-09-12

Applicant: Qualcomm Incorporated

Inventor： NHON TOAI QUACH ,  YANRU LI ,  WILLIAM EDWARD KIMBERLY

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4401 ,  G06F12/0284 ,  Y02D10/154

Abstract: A computing device and methods for exposing a solid-state non-volatile memory element to multiple masters in a computing device are disclosed. A portion of a solid-state non-volatile memory element includes code and data for use by a non-boot processing resource. A host controller in communication with the solid-state non-volatile memory element is modified to receive and respond to a resource identifier unique to the processing resource that is requesting read access to the solid-state non-volatile memory element. Logic executed by a boot master and logic executed by a non-boot processing resource are synchronized in response to a set of indicators.

Abstract translation: 公开了一种用于将固态非易失性存储元件暴露于计算设备中的多个主器件的计算设备和方法。 固态非易失性存储元件的一部分包括由非引导处理资源使用的代码和数据。 与固态非易失性存储器元件通信的主机控制器被修改为接收和响应正在请求对固态非易失性存储器元件的读访问的处理资源唯一的资源标识符。 由引导主机执行的逻辑和由非引导处理资源执行的逻辑被响应于一组指示符而被同步。

公开(公告)号：US20160196231A1

公开(公告)日：2016-07-07

申请号：US14591749

申请日：2015-01-07

Applicant: QUALCOMM INCORPORATED

Inventor： NHON TOAI QUACH ,  JEAN-MARIE QUOC DANH TRAN ,  NIKOLAI SCHLEGEL ,  JEAN-LOUIS TARDIEUX ,  BING XIAO

IPC: G06F13/40 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F13/4068 ,  G06F11/3027 ,  G06F11/3409

Abstract: Various embodiments of methods and systems for managing bus bandwidth allocation in a system on a chip are disclosed. Certain embodiments monitor a high speed bus for a measurement window of time to identify valid bits uniquely associated with transaction requests issued by a master processing engine. The method continues to monitor the bus over the window to identify completed transactions. A latency value is calculated by subtracting a target latency from an actual latency for each completed transaction. The latency value is aggregated in a counter. At the conclusion of the window, if the aggregated latency value is positive, the method may conclude that the average latency per transaction over the window exceeded the target latency per transaction and that the bandwidth allocated to the engine should be increased.

Abstract translation: 公开了用于在芯片上的系统中管理总线带宽分配的方法和系统的各种实施例。 某些实施例监视高速总线用于测量时间窗口，以识别与由主处理引擎发出的事务请求唯一相关联的有效位。 该方法继续监视窗口上的总线以识别已完成的事务。 通过从每个完成的交易的实际延迟中减去目标等待时间来计算延迟值。 延迟值汇总在计数器中。 在窗口结束时，如果聚合延迟值为正，则该方法可以得出结论，窗口上每事务的平均延迟超过每个事务的目标延迟，并且应该增加分配给引擎的带宽。

公开(公告)号：US20160148670A1

公开(公告)日：2016-05-26

申请号：US14616720

申请日：2015-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： NHON TOAI QUACH ,  VIRAT DEEPAK ,  OSCAR CABRAL ARIAS ,  YANRU LI ,  HAW-JING LO ,  MICHAEL DROP ,  VENKATA NARAYANA RAMESH PINNAMARAJU DURGA ,  MOINUL KHAN

IPC: G11C11/4074 ,  G06F1/32 ,  G11C11/409

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/401 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Abstract translation: 公开了用于减少便携式计算设备中的易失性存储器待机功率的系统和方法的各种实施例。 一种这样的方法包括接收对易失性存储器设备进入待机功率模式的请求。 确定一个或多个压缩参数以压缩存储在易失性存储器件的多个组中的内容。 存储的内容基于一个或多个压缩参数被压缩以释放多个存储体中的至少一个存储体。 该方法禁用在待机功率模式期间由压缩释放的多个组中的一个或多个的至少一部分的自刷新。