公开(公告)号：US20220190833A1

公开(公告)日：2022-06-16

申请号：US17117240

申请日：2020-12-10

Applicant: QUALCOMM INCORPORATED

Inventor： Masoud MOSLEHI BAJESTAN ,  Giovanni MARUCCI ,  Dongmin PARK ,  Marco ZANUSO ,  Yiwu TANG

IPC: H03L7/093 ,  H03K3/037 ,  H03M3/00

Abstract: A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.