公开(公告)号：US20170338940A1

公开(公告)日：2017-11-23

申请号：US15270444

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Marco ZANUSO ,  Mohammad ELBADRY ,  Tsai-Pi HUNG ,  Ravi SRIDHARA ,  Francesco GATTA ,  Jingcheng ZHUANG

IPC: H04L7/033 ,  H04L5/14 ,  H04L29/06 ,  H04W84/04

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

公开(公告)号：US20240106623A1

公开(公告)日：2024-03-28

申请号：US17935052

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Gang LIU ,  Xiaotie WU ,  Razak HOSSAIN ,  Marco ZANUSO ,  Yiwu TANG

IPC: H04L7/033 ,  H04L7/00 ,  H04W56/00

CPC classification number: H04L7/033 ,  H04L7/0033 ,  H04W56/0035

Abstract: Aspects described herein include devices and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having an analog 1-bit sampler configured to sample a phase locked loop (PLL) output signal using a PLL reference clock to generate 1-bit samples and a digital phase computation and control circuit configured to receive the 1-bit samples from the analog 1-bit sampler and apply phase corrections to the PLL based on a phase error derived from the 1-bit samples.

公开(公告)号：US20160065195A1

公开(公告)日：2016-03-03

申请号：US14471530

申请日：2014-08-28

Applicant: QUALCOMM Incorporated

Inventor： Mohammad FARAZIAN ,  Serkan SAYILIR ,  Marco ZANUSO ,  Yiwu TANG

IPC: H03K5/15 ,  H03H11/22 ,  H03H11/20

CPC classification number: H03K5/1506 ,  H03H11/22 ,  H03H19/002 ,  H03K2005/00286

Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating multiple oscillating signals having different phases. One example multiphase generating circuit generally includes a first phase shifting circuit configured to phase shift an input signal having an input frequency, such that an output signal of the first phase shifting circuit has a first phase difference with respect to the input signal; a first frequency dividing circuit configured to receive the input signal and output a first set of signals having a first frequency less than the input frequency of the input signal; and a second frequency dividing circuit configured to receive the output signal of the first phase shifting circuit and output a second set of signals having a second frequency less than the input frequency of the input signal. The multiphase signals may be used for fast frequency estimation of the input signal or in N-path filters.

Abstract translation: 本公开的某些方面提供了用于产生具有不同相位的多个振荡信号的方法和装置。 一个示例性多相生成电路通常包括：第一移相电路，被配置为使具有输入频率的输入信号相移，使得第一移相电路的输出信号相对于输入信号具有第一相位差; 第一分频电路，被配置为接收所述输入信号并输出​​具有小于所述输入信号的输入频率的第一频率的第一组信号; 以及第二分频电路，被配置为接收第一移相电路的输出信号并输出​​具有小于输入信号的输入频率的第二频率的第二组信号。 多相信号可用于输入信号的快速频率估计或N路径滤波器。

公开(公告)号：US20210044253A1

公开(公告)日：2021-02-11

申请号：US17076998

申请日：2020-10-22

Applicant: QUALCOMM INCORPORATED

Inventor： Yue CHAO ,  Yinghan WANG ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN

IPC: H03B5/12 ,  H03L7/093 ,  H03L7/08

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

公开(公告)号：US20170310458A1

公开(公告)日：2017-10-26

申请号：US15269320

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Marco ZANUSO ,  Giovanni MARUCCI ,  Tsai-Pi HUNG ,  Francesco GATTA ,  Bo SUN

IPC: H04L7/033 ,  H04W72/04 ,  H04B1/40

CPC classification number: H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

公开(公告)号：US20220190833A1

公开(公告)日：2022-06-16

申请号：US17117240

申请日：2020-12-10

Applicant: QUALCOMM INCORPORATED

Inventor： Masoud MOSLEHI BAJESTAN ,  Giovanni MARUCCI ,  Dongmin PARK ,  Marco ZANUSO ,  Yiwu TANG

IPC: H03L7/093 ,  H03K3/037 ,  H03M3/00

Abstract: A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

公开(公告)号：US20210072778A1

公开(公告)日：2021-03-11

申请号：US16561839

申请日：2019-09-05

Applicant: QUALCOMM Incorporated

Inventor： Yue CHAO ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN ,  Yiwu TANG

IPC: G05F1/575 ,  G05F1/595 ,  H03F3/45

Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

公开(公告)号：US20200091866A1

公开(公告)日：2020-03-19

申请号：US16132731

申请日：2018-09-17

Applicant: QUALCOMM INCORPORATED

Inventor： Yue CHAO ,  Yinghan WANG ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN

IPC: H03B5/12 ,  H03L7/093

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.