公开(公告)号：US20220075523A1

公开(公告)日：2022-03-10

申请号：US17405946

申请日：2021-08-18

Applicant: QUALCOMM INCORPORATED

Inventor： Baranidharan MUTHUKUMARAN ,  Hung Vuong ,  Satish Anand ,  Benish Babu

IPC: G06F3/06

Abstract: Data may be purged from a memory device in a manner confined to a particular partition of a memory device having two or more partitions. Logical memory blocks may be de-mapped from physical memory blocks of a first storage partition of the memory device. De-mapped physical memory blocks of the first storage partition may be listed in a local de-mapped block list uniquely associated with the first storage partition. A local purge command may be received from a host device. In response to the local purge command, at least a portion of the de-mapped physical memory blocks listed only in the local de-mapped block list are purged.

公开(公告)号：US10802736B2

公开(公告)日：2020-10-13

申请号：US16030841

申请日：2018-07-09

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Todd Christopher Reynolds ,  Hung Vuong

IPC: G06F3/06 ,  G11C5/14 ,  G06F1/3234 ,  G11C16/30 ,  G06F13/16

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

公开(公告)号：US11221774B2

公开(公告)日：2022-01-11

申请号：US17011720

申请日：2020-09-03

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Todd Christopher Reynolds ,  Hung Vuong

IPC: G06F3/06 ,  G11C5/14 ,  G06F1/3234 ,  G11C16/30 ,  G06F13/16

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

公开(公告)号：US10199115B2

公开(公告)日：2019-02-05

申请号：US15615827

申请日：2017-06-06

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Robert Hardacker ,  Hung Vuong

IPC: G11C16/04 ,  G11C16/34 ,  G06F12/02

Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.

公开(公告)号：US10558393B2

公开(公告)日：2020-02-11

申请号：US15789903

申请日：2017-10-20

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  David Teb ,  Hung Vuong

IPC: G06F3/06 ,  G06F12/02

Abstract: A system is proposed to enable a hardware based host controller to perform operations related to Host-aware Performance booster (HPB). The host controller may retrieve a command packet from a host memory targeting a logical address of a storage location of the storage device, may retrieve a physical address of the storage device mapped to the logical address from the address map, and may send the command packet to the storage device. The sent command packet may have the physical address incorporated therein.

公开(公告)号：US10360987B2

公开(公告)日：2019-07-23

申请号：US16175745

申请日：2018-10-30

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Robert Hardacker ,  Hung Vuong

IPC: G11C16/04 ,  G11C16/34 ,  G06F12/02

Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.

公开(公告)号：US20240319916A1

公开(公告)日：2024-09-26

申请号：US18187259

申请日：2023-03-21

Applicant: QUALCOMM Incorporated

Inventor： Hung Vuong ,  Benish Babu

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0604

Abstract: This disclosure provides systems, methods, and devices for memory systems that support updating a configuration of a physical layer interface (PHY) using information stored in a buffer of a connected memory system. In a first aspect, a method of accessing data in a flash memory system includes initializing, by a memory controller of a host device, a PHY for connecting the host device to a memory system to operate at a first speed, receiving PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed, from a first buffer of the memory system, and adjusting, by the memory controller, a configuration of the PHY in accordance with the PHY configuration information to operate at the second speed. Other aspects and features are also claimed and described.

公开(公告)号：US11029856B2

公开(公告)日：2021-06-08

申请号：US16287393

申请日：2019-02-27

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Hung Vuong

IPC: G06F3/06 ,  G06F11/30 ,  G06F12/02 ,  G11C16/06

Abstract: Methods and apparatuses to fragment data in a flash memory device are presented. The apparatus includes a host configured to request a flash memory device, via a memory bus, to fragment data stored in the flash memory device in response to a determination of a data fragmentation status of the flash memory device exceeding a threshold. The method includes determining a data fragmentation status of the flash memory device exceeding a threshold and requesting, by a host, the flash memory device to fragment data stored in the flash memory device in response to the determining the data fragmentation status exceeding the threshold.

公开(公告)号：US10510382B2

公开(公告)日：2019-12-17

申请号：US15782833

申请日：2017-10-12

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  David Teb ,  Hung Vuong ,  Venkatakrishnan Gopalakrishnan

IPC: G11C7/10 ,  G06F13/42 ,  G06F13/10 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.

公开(公告)号：US10444999B2

公开(公告)日：2019-10-15

申请号：US15292675

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  David Teb ,  Hung Vuong

IPC: G06F3/06 ,  G06F13/40

Abstract: Systems and method are directed to a Universal Flash Storage (UFS) host capable of interfacing one or more UFS devices. The UFS host includes a plurality of mobile-physical-layers (M-PHYs) for supporting one or more lanes of traffic between the UFS host and the one or more UFS devices. A Reference M-PHY MODULE Interface (RMMI) router is coupled between a Unified Protocol link layer (Unipro) and the plurality of M-PHYs. The RMMI router is configurable in a transparent mode to pass traffic, without routing, between the UFS host and a 2-lane embedded UFS device through the two M-PHYs. The RMMI router is configurable in a routing mode, to route traffic to a first M-PHY interfacing a 1-lane embedded UFS device or to a second M-PHY interfacing a 1-lane removable UFS card. The RMMI router is configurable based on metal strap or read only memory (ROM) setting.