公开(公告)号：US20210200679A1

公开(公告)日：2021-07-01

申请号：US17204534

申请日：2021-03-17

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund TURNER ,  George PATSILARAS ,  Bohuslav RYCHLIK ,  Wesley James HOLLAND ,  Jeffrey SHABEL ,  Simon Peter William BOOTH

IPC: G06F12/0846 ,  G06F12/02 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/1072 ,  G06F12/0868

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US20210174047A1

公开(公告)日：2021-06-10

申请号：US16703616

申请日：2019-12-04

Applicant: QUALCOMM Incorporated

Inventor： Wesley James HOLLAND ,  Rashmi KULKARNI ,  Ling Feng HUANG ,  Huang HUANG ,  Jeffrey SHABEL ,  Chih-Chi CHENG ,  Satish ANAND ,  Songhe CAI ,  Simon Peter William BOOTH ,  Bohuslav RYCHLIK

IPC: G06K9/00 ,  G06F21/32 ,  H04L9/32 ,  G01N21/31

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

公开(公告)号：US20190012271A1

公开(公告)日：2019-01-10

申请号：US15641765

申请日：2017-07-05

Applicant: QUALCOMM Incorporated

Inventor： Christophe AVOINNE ,  Samar ASBE ,  Thomas ZENG ,  Jean-Louis TARDIEUX ,  Jeffrey SHABEL ,  Azzedine TOUZNI

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/1009 ,  G06F1/32

Abstract: One feature pertains to an apparatus that includes a memory circuit, a system memory-management unit (SMMU), and a processing circuit. The memory circuit stores an executable program associated with a client. The SMMU enforces memory access control policies for the memory circuit, and includes a plurality of micro-translation lookaside buffers (micro-TLBs), macro-TLB, and a page walker circuit. The plurality of micro-TLBs include a first micro-TLB that enforces memory access control policies for the client. The processing circuit loads memory address translations associated with the executable program into the first micro-TLB, and initiates isolation mode for the first micro-TLB causing communications between the first micro-TLB and the macro-TLB and between the first micro-TLB and the page walker circuit to be severed. The first micro-TLB continues to enforce memory access control policies for the client while in isolation mode.

公开(公告)号：US20210049099A1

公开(公告)日：2021-02-18

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： ANDREW EDMUND TURNER ,  George PATSILARAS ,  Bohuslav RYCHLIK ,  Wesley James HOLLAND ,  Jeffrey SHABEL ,  Simon Peter William BOOTH

IPC: G06F12/0846 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.