公开(公告)号：US20150127866A1

公开(公告)日：2015-05-07

申请号：US14072201

申请日：2013-11-05

Applicant: Qualcomm Incorporated

Inventor： Thomas ZENG ,  Samar Asbe ,  Azzedine Touzni

IPC: G06F13/26 ,  G06F9/455 ,  G06F13/24

CPC classification number: G06F13/26 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4812 ,  G06F13/24 ,  G06F2009/45579

Abstract: Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

Abstract translation: 方面包括用于安全，快速和正常的虚拟中断直接分配的装置和方法，其通过包括可信（安全）和非安全执行环境的多个执行环境的处理器管理安全和非安全的虚拟和物理中断。 中断控制器可以识别中断的安全组值，并将可靠执行环境直接安全中断。 中断控制器可以识别非安全中断的直接分配值，指示非安全中断是由高级操作系统（HLOS）来宾还是虚拟机管理器（VMM）拥有，以及它是快速还是快速 一个正常的虚拟中断。 在绕过VMM时，中断控制器可以将HLOS Guest拥有的中断指向HLOS Guest。 当HLOS访客不可用时，中断可能被定向到VMM，以尝试将中断传递给HLOS访客，直到成功。

公开(公告)号：US20190012271A1

公开(公告)日：2019-01-10

申请号：US15641765

申请日：2017-07-05

Applicant: QUALCOMM Incorporated

Inventor： Christophe AVOINNE ,  Samar ASBE ,  Thomas ZENG ,  Jean-Louis TARDIEUX ,  Jeffrey SHABEL ,  Azzedine TOUZNI

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/1009 ,  G06F1/32

Abstract: One feature pertains to an apparatus that includes a memory circuit, a system memory-management unit (SMMU), and a processing circuit. The memory circuit stores an executable program associated with a client. The SMMU enforces memory access control policies for the memory circuit, and includes a plurality of micro-translation lookaside buffers (micro-TLBs), macro-TLB, and a page walker circuit. The plurality of micro-TLBs include a first micro-TLB that enforces memory access control policies for the client. The processing circuit loads memory address translations associated with the executable program into the first micro-TLB, and initiates isolation mode for the first micro-TLB causing communications between the first micro-TLB and the macro-TLB and between the first micro-TLB and the page walker circuit to be severed. The first micro-TLB continues to enforce memory access control policies for the client while in isolation mode.