公开(公告)号：US20140089598A1

公开(公告)日：2014-03-27

申请号：US13626916

申请日：2012-09-26

Applicant: QUALCOMM INCORPORATED

Inventor： Leslie Mark DeBruyne ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel

IPC: G06F12/08

CPC classification number: G06F12/0886 ,  G06F9/30149 ,  G06F9/3816 ,  G06F12/0888 ,  G06F12/10 ,  G06F2212/452

Abstract: An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.

Abstract translation: 具有可高速缓存的第一部分的指令高速缓存行中的指令，来自不可缓存的页面的第二部分和跨越高速缓存行的指令被禁止从指令高速缓存执行。 与不可缓存的第二部分相关联的属性与高速缓存行中的其余指令的属性分开跟踪。 如果到达执行页面交叉指令，则刷新页面交叉指令和指令，并且对至少第二部分对存储器进行不可缓存请求。 一旦接收到第二部分，则从保存在先前取出组中的第一部分重构整个页面交叉指令。 返回页面交叉指令或其一部分具有用于非缓存取出指令的适当属性，并且重建的指令可以被执行而不被缓存。

公开(公告)号：US08819342B2

公开(公告)日：2014-08-26

申请号：US13626916

申请日：2012-09-26

Applicant: QUALCOMM Incorporated

Inventor： Leslie Mark DeBruyne ,  James Norris Dieffenderfer ,  Michael Scott Mcilvaine ,  Brian Michael Stempel

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F12/0886 ,  G06F9/30149 ,  G06F9/3816 ,  G06F12/0888 ,  G06F12/10 ,  G06F2212/452

Abstract: An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.

Abstract translation: 具有可高速缓存的第一部分的指令高速缓存行中的指令，来自不可缓存的页面的第二部分和跨越高速缓存行的指令被禁止从指令高速缓存执行。 与不可缓存的第二部分相关联的属性与高速缓存行中的其余指令的属性分开跟踪。 如果到达执行页面交叉指令，则刷新页面交叉指令和指令，并且对至少第二部分对存储器进行不可缓存请求。 一旦接收到第二部分，则从保存在先前取出组中的第一部分重构整个页面交叉指令。 返回页面交叉指令或其一部分具有用于非缓存取出指令的适当属性，并且重建的指令可以被执行而不被缓存。

公开(公告)号：US20130326195A1

公开(公告)日：2013-12-05

申请号：US13787907

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Brian Michael Stempel ,  Leslie Mark DeBruyne ,  Melinda J. Brown

IPC: G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30145 ,  G06F9/3017 ,  G06F11/1064

Abstract: Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media are disclosed. In this regard, a method for processing instructions in a central processing unit (CPU) is provided. The method comprises decoding an instruction comprising a plurality of bits, and generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. If the parity error indicator indicates that the parity error exists in the plurality of bits, one or more of the plurality of bits are modified to indicate a no execution operation (NOP), without effecting a roll back of a program counter of the CPU and without re-decoding the instruction. In this manner, the possibility of the parity error causing an inadvertent execution of an unpredictable instruction is reduced.

Abstract translation: 公开了防止奇偶校验错误引起的不可预测指令的执行以及相关的处理器系统，方法和计算机可读介质。 在这方面，提供了一种用于处理中央处理单元（CPU）中的指令的方法。 该方法包括对包含多个比特的指令进行解码，并产生一个奇偶校验错误指示符，该奇偶校验错误指示符指示执行指令之前多个比特中是否存在奇偶校验错误。 如果奇偶校验错误指示符表示多个比特中存在奇偶校验错误，则修改多个比特中的一个或多个，以指示不执行操作（NOP），而不影响CPU的程序计数器的回退，并且 无需重新解码指令。 以这种方式，减少了导致无意中执行不可预测指令的奇偶校验错误的可能性。