公开(公告)号：US20240421918A1

公开(公告)日：2024-12-19

申请号：US18337256

申请日：2023-06-19

Applicant: Qualcomm Incorporated

Inventor： Shilei Hao ,  Dongling Pan ,  Rui Xu ,  Yiwu Tang

IPC: H04B17/00 ,  H03L7/099

Abstract: An apparatus is disclosed that implements an on-chip test tone generator for built-in spur testing. In an example aspect, the apparatus includes an integrated circuit with a test tone generator, at least one reference signal generator, and at least one signal propagation path. The test tone generator includes an amplitude control circuit. The at least one signal propagation path includes a transceiver path, a mixer, and a switch. The transceiver path is configured to be coupled to an antenna. The mixer has a first input coupled to the at least one reference signal generator. The switch is configured to selectively couple a second input of the mixer to the transceiver path or the amplitude control circuit of the at least one test tone generator.

公开(公告)号：US11349483B1

公开(公告)日：2022-05-31

申请号：US17391406

申请日：2021-08-02

Applicant: QUALCOMM INCORPORATED

Inventor： Shilei Hao ,  Yunliang Zhu ,  Yiwu Tang ,  Dongmin Park

IPC: H03K23/00 ,  H03K23/44 ,  H03K3/356 ,  H03K21/10 ,  H03K23/40

Abstract: A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.