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公开(公告)号：US20220352878A1
公开(公告)日：2022-11-03
申请号：US17238173
申请日：2021-04-22
Applicant: Qualcomm Incorporated
Inventor： Yan Zhang , Yunliang Zhu , Yiwu Tang
Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.
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公开(公告)号：US10291242B1
公开(公告)日：2019-05-14
申请号：US15993254
申请日：2018-05-30
Applicant: QUALCOMM Incorporated
Inventor： Mohammad Elbadry , Marco Zanuso , Tsai-Pi Hung , Francesco Gatta , Yunliang Zhu
Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.
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公开(公告)号：US11349483B1
公开(公告)日：2022-05-31
申请号：US17391406
申请日：2021-08-02
Applicant: QUALCOMM INCORPORATED
Inventor： Shilei Hao , Yunliang Zhu , Yiwu Tang , Dongmin Park
Abstract: A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.
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Patent Agency Ranking
公开(公告)号：US20140266471A1
公开(公告)日：2014-09-18
申请号：US13837463
申请日：2013-03-15
Applicant: QUALCOMM INCORPORATED
Inventor： Yunliang Zhu , Yiwu Tang
IPC: H03L7/00
CPC classification number: H03L7/00 , H03B19/14 , H03B27/00 , H03K3/0315 , H03K3/0322 , H03L7/18 , H03L7/24 , H04B1/40
Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.
Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置产生LO信号。 该装置包括耦合在一起的LO发生器模块和注入信号发生器模块。 LO发生器模块具有多个LO输出和多个注入信号输入。 LO模块被配置为基于在注入信号输入端接收到的注入信号，在LO输出端产生LO信号。 注入信号发生器模块具有多个LO输入和多个注入信号输出。 LO输入耦合到LO输出。 注入信号输出耦合到注入信号输入端。 注入信号发生器模块被配置为基于在LO输入上接收的LO信号并且基于接收的VCO信号，在喷射信号输出上产生喷射信号。
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公开(公告)号：US11677390B2
公开(公告)日：2023-06-13
申请号：US17238173
申请日：2021-04-22
Applicant: Qualcomm Incorporated
Inventor： Yan Zhang , Yunliang Zhu , Yiwu Tang
CPC classification number: H03K5/00006 , H03B5/1221 , H03B19/10 , H03B19/14 , H03D7/14 , H04B1/0483 , H04L27/362
Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.
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公开(公告)号：US09106234B2
公开(公告)日：2015-08-11
申请号：US13837463
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Yunliang Zhu , Yiwu Tang
CPC classification number: H03L7/00 , H03B19/14 , H03B27/00 , H03K3/0315 , H03K3/0322 , H03L7/18 , H03L7/24 , H04B1/40
Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.
Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置产生LO信号。 该装置包括耦合在一起的LO发生器模块和注入信号发生器模块。 LO发生器模块具有多个LO输出和多个注入信号输入。 LO模块被配置为基于在注入信号输入端接收到的注入信号，在LO输出端产生LO信号。 注入信号发生器模块具有多个LO输入和多个注入信号输出。 LO输入耦合到LO输出。 注入信号输出耦合到注入信号输入端。 注入信号发生器模块被配置为基于在LO输入上接收的LO信号并且基于接收的VCO信号，在喷射信号输出上产生喷射信号。
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公开(公告)号：US11342927B1
公开(公告)日：2022-05-24
申请号：US17361217
申请日：2021-06-28
Applicant: QUALCOMM Incorporated
Inventor： Younghyun Lim , Yiwu Tang , Dongmin Park , Yunliang Zhu , Mustafa Keskin , Yue Chao
Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.
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公开(公告)号：US11264995B1
公开(公告)日：2022-03-01
申请号：US17079795
申请日：2020-10-26
Applicant: QUALCOMM INCORPORATED
Inventor： Yue Chao , Yiwu Tang , Yunliang Zhu , Dongmin Park , Jingcheng Zhuang
Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.
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