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    On-Chip Test Tone Generator for Built-In Spur Testing
    1.
    发明申请
    On-Chip Test Tone Generator for Built-In Spur Testing 有权

    公开(公告)号：US20240421918A1

    公开(公告)日：2024-12-19

    申请号：US18337256

    申请日：2023-06-19

    Applicant: Qualcomm Incorporated

    Inventor： Shilei Hao ,  Dongling Pan ,  Rui Xu ,  Yiwu Tang

    IPC: H04B17/00 ,  H03L7/099

    Abstract: An apparatus is disclosed that implements an on-chip test tone generator for built-in spur testing. In an example aspect, the apparatus includes an integrated circuit with a test tone generator, at least one reference signal generator, and at least one signal propagation path. The test tone generator includes an amplitude control circuit. The at least one signal propagation path includes a transceiver path, a mixer, and a switch. The transceiver path is configured to be coupled to an antenna. The mixer has a first input coupled to the at least one reference signal generator. The switch is configured to selectively couple a second input of the mixer to the transceiver path or the amplitude control circuit of the at least one test tone generator.

    Multimode Frequency Multiplier
    2.
    发明申请
    Multimode Frequency Multiplier 有权

    公开(公告)号：US20220352878A1

    公开(公告)日：2022-11-03

    申请号：US17238173

    申请日：2021-04-22

    Applicant: Qualcomm Incorporated

    Inventor： Yan Zhang ,  Yunliang Zhu ,  Yiwu Tang

    IPC: H03K5/00 ,  H03B19/14 ,  H03B19/10 ,  H04B1/04 ,  H04L27/36

    Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

    Phase interpolation-based fractional-N sampling phase-locked loop
    3.
    发明授权
    Phase interpolation-based fractional-N sampling phase-locked loop 有权

    公开(公告)号：US11411567B2

    公开(公告)日：2022-08-09

    申请号：US17117240

    申请日：2020-12-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： Masoud Moslehi Bajestan ,  Giovanni Marucci ,  Dongmin Park ,  Marco Zanuso ,  Yiwu Tang

    IPC: H03L7/099 ,  H03J7/04 ,  H03L7/02 ,  H03L7/093 ,  H03M3/00 ,  H03K3/037

    Abstract: A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

    P-type metal-oxide-semiconductor (PMOS) low drop-out (LDO) regulator
    4.
    发明授权
    P-type metal-oxide-semiconductor (PMOS) low drop-out (LDO) regulator 有权

    公开(公告)号：US10990117B2

    公开(公告)日：2021-04-27

    申请号：US16561839

    申请日：2019-09-05

    Applicant: QUALCOMM Incorporated

    Inventor： Yue Chao ,  Marco Zanuso ,  Rajagopalan Rangarajan ,  Yiwu Tang

    IPC: G05F1/575 ,  G05F1/595

    Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

    LOW POWER CURRENT RE-USING TRANSFORMER-BASED DUAL-BAND VOLTAGE CONTROLLED OSCILLATOR
    5.
    发明申请
    LOW POWER CURRENT RE-USING TRANSFORMER-BASED DUAL-BAND VOLTAGE CONTROLLED OSCILLATOR 有权
    低功耗电流重新使用基于变压器的双电压控制振荡器

    公开(公告)号：US20160373057A1

    公开(公告)日：2016-12-22

    申请号：US14745033

    申请日：2015-06-19

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Farazian ,  Masoud Moslehi Bajestan ,  Yiwu Tang ,  Jong Min Park ,  Sujiang Rong

    IPC: H03B5/12

    CPC classification number: H03B5/124 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1256 ,  H03B5/1296 ,  H03B2200/0072 ,  H03L7/099

    Abstract: A dual-band voltage controlled oscillator (VCO) includes: a first oscillator circuit including a first inductor; a second oscillator circuit including a second inductor; a first mode switch configured to electrically connect or disconnect a first output terminal of the first oscillator circuit and a first output terminal of the second oscillator circuit; a second mode switch configured to electrically connect or disconnect a second output terminal of the first oscillator circuit and a second output terminal of the second oscillator circuit; a third mode switch configured to electrically connect or disconnect a first terminal of the first inductor and a first terminal of the second inductor; and a fourth mode switch configured to electrically connect or disconnect a second terminal of the first inductor and a second terminal of the second inductor.

    Abstract translation: 双频带压控振荡器（VCO）包括：第一振荡器电路，包括第一电感器; 包括第二电感器的第二振荡器电路; 第一模式开关，被配置为电连接或断开第一振荡电路的第一输出端和第二振荡电路的第一输出端; 第二模式开关，被配置为电连接或断开第一振荡电路的第二输出端和第二振荡电路的第二输出端; 第三模式开关，被配置为电连接或断开第一电感器的第一端子和第二电感器的第一端子; 以及第四模式开关，被配置为电连接或断开第一电感器的第二端子和第二电感器的第二端子。

    Ring oscillator based frequency divider
    9.
    发明授权
    Ring oscillator based frequency divider 有权

    公开(公告)号：US11342927B1

    公开(公告)日：2022-05-24

    申请号：US17361217

    申请日：2021-06-28

    Applicant: QUALCOMM Incorporated

    Inventor： Younghyun Lim ,  Yiwu Tang ,  Dongmin Park ,  Yunliang Zhu ,  Mustafa Keskin ,  Yue Chao

    IPC: H03L7/099 ,  H03K21/08 ,  H03K23/66 ,  H03L7/191

    Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

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