公开(公告)号：US20170220268A1

公开(公告)日：2017-08-03

申请号：US15077879

申请日：2016-03-22

Applicant: QUALCOMM INCORPORATED

Inventor： VALMICK GUHA ,  Narasimhan Agaram ,  Ranjith Kumar Narahari ,  Dexter Chun

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0649 ,  G06F3/0688 ,  G06F12/0246

Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.