公开(公告)号：US10817224B2

公开(公告)日：2020-10-27

申请号：US15191400

申请日：2016-06-23

Applicant: QUALCOMM INCORPORATED

Inventor： Subrato Kumar De ,  Dexter Chun ,  Yanru Li

IPC: G06F3/06 ,  G06F9/445 ,  G06F12/02 ,  G06F8/61

Abstract: Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.

公开(公告)号：US20180052785A1

公开(公告)日：2018-02-22

申请号：US15243435

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Chun ,  Haw-Jing Lo

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1673 ,  Y02D10/14

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

公开(公告)号：US20170220268A1

公开(公告)日：2017-08-03

申请号：US15077879

申请日：2016-03-22

Applicant: QUALCOMM INCORPORATED

Inventor： VALMICK GUHA ,  Narasimhan Agaram ,  Ranjith Kumar Narahari ,  Dexter Chun

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0649 ,  G06F3/0688 ,  G06F12/0246

Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.

公开(公告)号：US10783252B2

公开(公告)日：2020-09-22

申请号：US16107956

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Azzedine Touzni ,  Dexter Chun

IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G06F9/445 ,  G06F9/4401 ,  G06F21/51 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F15/78

Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.

公开(公告)号：US10558369B2

公开(公告)日：2020-02-11

申请号：US15077879

申请日：2016-03-22

Applicant: QUALCOMM INCORPORATED

Inventor： Valmick Guha ,  Narasimhan Agaram ,  Ranjith Kumar Narahari ,  Dexter Chun

IPC: G06F3/06 ,  G06F12/02

Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.

公开(公告)号：US10394724B2

公开(公告)日：2019-08-27

申请号：US15243435

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Chun ,  Haw-Jing Lo

IPC: G06F13/00 ,  G06F13/16

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

公开(公告)号：US20190065752A1

公开(公告)日：2019-02-28

申请号：US16107956

申请日：2018-08-21

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Azzedine Touzni ,  Dexter Chun

IPC: G06F21/57 ,  G06F1/32 ,  G06F15/78

Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.

公开(公告)号：US11024361B2

公开(公告)日：2021-06-01

申请号：US15400507

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Jungwon Suh

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4091 ,  G11C8/12

Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

公开(公告)号：US10296069B2

公开(公告)日：2019-05-21

申请号：US15634956

申请日：2017-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Richard Stewart ,  Dexter Chun

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3237 ,  G06F13/16 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/3225 ,  G06F1/324

Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.

公开(公告)号：US09864536B2

公开(公告)日：2018-01-09

申请号：US14062859

申请日：2013-10-24

Applicant: Qualcomm Incorporated

Inventor： Dexter Chun ,  Haw-Jing Lo

IPC: G06F3/06 ,  H03M7/40 ,  H03M7/30

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  H03M7/40 ,  H03M7/6047

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.