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公开(公告)号:US20210058076A1
公开(公告)日:2021-02-25
申请号:US16548517
申请日:2019-08-22
Applicant: QUALCOMM Incorporated
Inventor: Andi ZHAO , Ramaprasath VILANGUDIPITCHAI , Hyeokjin LIM , Seung Hyuk KANG
Abstract: A hybrid fin flip flop circuit may comprise a mixture of 1-fin transistors and multi-fin transistors. In one example, a flip flop circuit may comprise 1-fin transistors in at least one of the critical paths of the flip flop circuit such as the drive circuit, the input circuit, or the output circuit. In one example, a flip flop circuit may include: an input circuit; a clock driver circuit; an output circuit; and a latch circuit; wherein one of the input circuit, the clock driver circuit, or the output circuit comprises a multi-fin transistor and the latch circuit comprises a plurality of 1-fin transistors.
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公开(公告)号:US20180145071A1
公开(公告)日:2018-05-24
申请号:US15360777
申请日:2016-11-23
Applicant: QUALCOMM Incorporated
Inventor: Andi ZHAO , Ramaprasath VILANGUDIPITCHAI , Dorav KUMAR
IPC: H01L27/088 , H01L23/528 , H01L23/522 , H01L27/02 , H03K17/16
CPC classification number: H01L27/088 , H01L23/5222 , H01L23/5223 , H01L23/5228 , H01L23/528 , H01L27/0207 , H01L27/0629 , H01L29/94 , H03K17/162
Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.
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