公开(公告)号：US20180145071A1

公开(公告)日：2018-05-24

申请号：US15360777

申请日：2016-11-23

Applicant: QUALCOMM Incorporated

Inventor： Andi ZHAO ,  Ramaprasath VILANGUDIPITCHAI ,  Dorav KUMAR

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H03K17/16

CPC classification number: H01L27/088 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/94 ,  H03K17/162

Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.

公开(公告)号：US20150262936A1

公开(公告)日：2015-09-17

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta BANSAL ,  Uday DODDANNAGARI ,  Paras GUPTA ,  Ramaprasath VILANGUDIPITCHAI ,  Parissa NAJDESAMII ,  Dorav KUMAR ,  Nitin PARTANI

IPC: H01L23/538 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。

公开(公告)号：US20180158506A1

公开(公告)日：2018-06-07

申请号：US15370892

申请日：2016-12-06

Applicant: QUALCOMM Incorporated

Inventor： Dorav KUMAR ,  Venkat NARAYANAN ,  Bilal ZAFAR ,  Seid Hadi RASOULI ,  Venugopal BOYNAPALLI

IPC: G11C11/4094 ,  G11C11/4076 ,  G06F1/12 ,  G06F1/06

CPC classification number: G11C11/4094 ,  G06F1/06 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/222 ,  G11C11/4076

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.

公开(公告)号：US20170373689A1

公开(公告)日：2017-12-28

申请号：US15192872

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Dorav KUMAR ,  Venkatasubramanian NARAYANAN ,  Bala Krishna THALLA ,  Seid Hadi RASOULI ,  Radhika Vinayak GUTTAL ,  Sivakumar PATURI

IPC: H03K19/003 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088

CPC classification number: H03K19/00361 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H03K19/17736 ,  H03K19/17744

Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.