公开(公告)号：US20160025776A1

公开(公告)日：2016-01-28

申请号：US14340387

申请日：2014-07-24

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Chang-Ho LEE

IPC: G01R1/067 ,  G01R31/28 ,  G01R1/073

CPC classification number: G01R1/06722 ,  G01R1/07314 ,  G01R31/2851

Abstract: In one aspect, a probe assembly for probing an IC is provided. The probe assembly includes a probe, which includes a probe head for contacting the integrated circuit and a body. The probe head is elongated in a first direction. The body includes a spring and an edge portion contacting the probe head. One conductor extends in a second direction and is configured to connect to a voltage potential. An electric field between the probe and the at least one conductor is perpendicular to a magnetic field of the probe. In another aspect, a probe assembly includes a first probe and second probe. Each of the first probe and the second probe is elongated in a first direction and is configured to contact an IC. A conductor extends in a second direction is provided between the first probe and the second probe. The conductor is connected to a voltage potential.

Abstract translation: 一方面，提供了用于探测IC的探针组件。 探针组件包括探针，其包括用于接触集成电路的探头和主体。 探头在第一方向上伸长。 主体包括弹簧和与探头接触的边缘部分。 一个导体沿第二方向延伸并被配置为连接到电压电位。 探针和至少一个导体之间的电场垂直于探针的磁场。 在另一方面，探针组件包括第一探针和第二探针。 第一探针和第二探针中的每一个在第一方向上是细长的并且被配置为接触IC。 在第一探针和第二探针之间设置沿第二方向延伸的导体。 导体连接到电压电位。

公开(公告)号：US20210098320A1

公开(公告)日：2021-04-01

申请号：US16590299

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Daniel GARCIA ,  Kinfegebriel Amera MENGISTIE ,  Francesco CARRARA ,  Chang-Ho LEE ,  Ashish ALAWANI ,  Mark KUHLMAN ,  John Jong-Hoon LEE ,  Jeongkeun KIM ,  Xiaoju YU ,  Supatta NIRAMARNKARN

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.