公开(公告)号：US11289495B1

公开(公告)日：2022-03-29

申请号：US17038037

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Biradar ,  Sunil Sharma ,  Channappa Desai ,  Sonia Ghosh

IPC: H01L27/11 ,  G11C11/419 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.

公开(公告)号：US10839866B1

公开(公告)日：2020-11-17

申请号：US16430137

申请日：2019-06-03

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Rahul Sahu ,  Channappa Desai

IPC: G11C5/14 ,  H03K17/28 ,  H03K17/30

Abstract: A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core.

公开(公告)号：US11469239B1

公开(公告)日：2022-10-11

申请号：US17217067

申请日：2021-03-30

Applicant: QUALCOMM Incorporated

Inventor： Channappa Desai ,  Sunil Sharma ,  Anne Srikanth ,  Pradeep Jayadev Kodlipet ,  Yandong Gao

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/482

Abstract: An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.

公开(公告)号：US20220320114A1

公开(公告)日：2022-10-06

申请号：US17217067

申请日：2021-03-30

Applicant: QUALCOMM Incorporated

Inventor： Channappa Desai ,  Sunil Sharma ,  Anne Srikanth ,  Pradeep Jayadev Kodlipet ,  Yandong Gao

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/482

Abstract: An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.

公开(公告)号：US11424250B2

公开(公告)日：2022-08-23

申请号：US17004457

申请日：2020-08-27

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Oruganti ,  Sreeram Gurram ,  Venkata Balakrishna Reddy Thumu ,  Pradeep Jayadev Kodlipet ,  Diwakar Singh ,  Channappa Desai ,  Sunil Sharma ,  Anne Srikanth ,  Yandong Gao

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/423

Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.

公开(公告)号：US20220102360A1

公开(公告)日：2022-03-31

申请号：US17038037

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Biradar ,  Sunil Sharma ,  Channappa Desai ,  Sonia Ghosh

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  G11C11/419

Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.