公开(公告)号：US11600307B2

公开(公告)日：2023-03-07

申请号：US17136616

申请日：2020-12-29

Applicant: QUALCOMM Incorporated

Inventor： David Li ,  Rahul Biradar ,  Biju Manakkam Veetil ,  Po-Hung Chen ,  Ayan Paul ,  Sung Son ,  Shivendra Kushwaha ,  Ravindra Reddy Chekkera ,  Derek Yang

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US20220102360A1

公开(公告)日：2022-03-31

申请号：US17038037

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Biradar ,  Sunil Sharma ,  Channappa Desai ,  Sonia Ghosh

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  G11C11/419

Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.

公开(公告)号：US11251123B1

公开(公告)日：2022-02-15

申请号：US17002486

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Sunil Sharma ,  Rahul Biradar ,  Sonia Ghosh

IPC: H01L23/528 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/522

Abstract: Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.

公开(公告)号：US11908537B2

公开(公告)日：2024-02-20

申请号：US18163146

申请日：2023-02-01

Applicant: QUALCOMM Incorporated

Inventor： David Li ,  Rahul Biradar ,  Biju Manakkam Veetil ,  Po-Hung Chen ,  Ayan Paul ,  Sung Son ,  Shivendra Kushwaha ,  Ravindra Reddy Chekkera ,  Derek Yang

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C5/025 ,  G11C7/06 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US11289495B1

公开(公告)日：2022-03-29

申请号：US17038037

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Biradar ,  Sunil Sharma ,  Channappa Desai ,  Sonia Ghosh

IPC: H01L27/11 ,  G11C11/419 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.

公开(公告)号：US11222846B1

公开(公告)日：2022-01-11

申请号：US17002486

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Sunil Sharma ,  Rahul Biradar ,  Sonia Ghosh

IPC: H01L23/528 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/522

Abstract: Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.